Specifications

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
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INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart
Table 5. Interrupt Mapping
Note
1. Configurable by option byte.
N°
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
Address
Vector
RESET Reset
N/A
Highest
Priority
Lowest
Priority
yes FFFEh-FFFFh
TRAP Software Interrupt no FFFCh-FFFDh
0 ei0 External Interrupt Port A7..0 (C5..0
1
)
yes
FFFAh-FFFBh
1 ei1 External Interrupt Port B7..0 (C5..0
1
) FFF8h-FFF9h
2 CSS Clock Security System Interrupt CRSR
no
FFF6h-FFF7h
3 SPI SPI Peripheral Interrupts SPISR FFF4h-FFF5h
4 TIMER A TIMER A Peripheral Interrupts TASR FFF2h-FFF3h
5 Not used FFF0h-FFF1h
6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh-FFEFh
7 Not used FFECh-FFEDh
8 Not used FFEAh-FFEBh
9 Not used FFE8h-FFE9h
10 Not used FFE6h-FFE7h
11 I²C I²C Peripheral Interrupt I2CSRx no FFE4h-FFE5h
12 Not Used FFE2h-FFE3h
13 Not Used FFE0h-FFE1h
I BIT SET?
Y
N
IRET?
Y
N
FROM RESET
LOAD PC FROM INTERRUPT VECTOR
STACK PC, X, A, CC
SET I BIT
FETCH NEXT INSTRUCTION
EXECUTE INSTRUCTION
THIS CLEARS I BIT BY DEFAULT
RESTORE PC, X, A, CC FROM STACK
INTERRUPT
Y
N
PENDING?