Specifications

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
36/141
10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in
-
terrupts or the I/O alternate functions.
10.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows having two ful
-
ly independent external interrupt source sensitivi-
ties with configurable sources (using EXTIT option
bit) as shown in
Figure 23 and Figure 24.
Each external interrupt source can be generated
on four different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter
-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
10.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■ Main clock signal (f
CPU
) output on PC2
■ SPI pin configuration:
– SS pin internal control to use the PB7 I/O port
function while the SPI is active.
– Master output capability on MOSI pin (PB4)
deactivated while the SPI is active.
– Slave output capability on MISO pin (PB5) de-
activated while the SPI is active.
These functions are described in detail in the Sec-
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 37.
Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)
Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)
ei0
INTERRUPT
SOURCE
IS00 IS01
MISCR1
SENSITIVITY
CONTROL
PA7
PA0
PC5
PC0
PB7
PB0
IS10 IS11
MISCR1
SENSITIVITY
CONTROL
ei1
INTERRUPT
SOURCE
PA7
PA0
IS00 IS01
MISCR1
SENSITIVITY
CONTROL
ei0
INTERRUPT
SOURCE
ei1
INTERRUPT
SOURCE
IS10 IS11
MISCR1
SENSITIVITY
CONTROL
PB7
PB0
PC5
PC0