Specifications

ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
77/141
I
2
C BUS INTERFACE (Cont’d)
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter
-
nal shift register.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 3 Transfer sequencing
EV8).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener
-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
Note that BERR will not be set if an error is de-
tected during the first pulse of each 9-bit transac-
tion:
Single Master Mode
If a Start or Stop is issued during the first pulse of
a 9-bit transaction, the BERR flag will not be set
and transfer will continue however the BUSY flag
will be reset. To work around this, slave devices
should issue a NACK when they receive a mis
-
placed Start or Stop. The reception of a NACK or
BUSY by the master in the middle of communica
-
tion gives the possibility to reinitiate transmis-
sion.
Multimaster Mode
Normally the BERR bit would be set whenever
unauthorized transmission takes place while
transfer is already in progress. However, an is
-
sue will arise if an external master generates an
unauthorized Start or Stop while the I
2
C master
is on the first pulse pulse of a 9-bit transaction. It
is possible to work around this by polling the
BUSY bit during I
2
C master mode transmission.
The resetting of the BUSY bit can then be han
-
dled in a similar manner as the BERR flag being
set.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft
-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
Note: In all these cases, the SCL line is not held
low; however,the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary
to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or
BTF) that are set at the same time.