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File Number 4868.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ISL3873

Wireless LAN Integrated Medium Access

Controller with Baseband Processor

The Intersil ISL3873 Wireless LAN

Integrated Medium Access Controller

with Integrated Baseband Processor

is part of the PRISM® 2.4GHz radio

chip set. The ISL3873 directly interfaces with the Intersil’s IF

QMODEM (HFA3783). Adding Intersil’s RF/IF Converter

(ISL3685) and Intersil’s Power Amp (HFA3983) offers the

designer a complete end-to-end WLAN Chip Set solution.

Protocol and PHY support are implemented in ﬁrmware

thus, supporting customization of the WLAN solution.

Firmware implements the full IEEE 802.11 Wireless LAN

MAC protocol. It supports BSS and IBSS operation under

DCF, and operation under the optional Point Coordination

Function (PCF). Low level protocol functions such as

RTS/CTS generation and acknowledgment, fragmentation

and de-fragmentation, and automatic beacon monitoring are

handled without host intervention. Active scanning is

performed autonomously once initiated by host command.

Host interface command and status handshakes allow

concurrent operations from multi-threaded I/O drivers.

Additional ﬁrmware functions speciﬁc to access point

applications are also available.

The ISL3873 has on-board A/Ds and D/A for analog I and Q

inputs and outputs, for which the HFA3783 IF QMODEM is

recommended. Differential phase shift keying modulation

schemes DBPSK and DQPSK, with data scrambling

capability, are available along with Complementary Code

Keying to provide a variety of data rates. Both Receive and

Transmit AGC functions with 7-bit AGC control obtain

maximum performance in the analog portions of the

transceiver.

Built-in ﬂexibility allows the ISL3873 to be conﬁgured

through a general purpose control bus, for a range of

applications. The ISL3873 is housed in a thin plastic BGA

package suitable for PCMCIA board applications.

The ISL3873 is designed to provide maximum performance

with minimum power consumption. External pin layout is

organized to provide optimal PC board layout to all user

interfaces including PCMCIA and USB.

New Features of the ISL3873

• USB Host Interface Supports USB V1.1 at 12Mbps.

• New Start Up Modes Allow the PCMCIA Card Information

Structure to be Initialized From a Serial EEPROM. This

Allows Firmware to be Downloaded from the Host,

Eliminating the Parallel Flash Memory Device

• Firmware Can be Loaded from Serial Flash Memory

• Zero Glue Connection to 16-Bit Wide SRAM Devices

• Low Frequency Crystal Oscillator to Maintain Time and

Allow Baseband Clock Source to Power off During Sleep

Mode

• Improved Performance of Internal WEP Engine

• Improvements to Debug Mode Support Tracing Execution

From on Chip Memory

• Programmable MBUS Cycle Extension Allows Accessing

of Slow Memory Devices Without Slowing the Clock

• Complete DSSS Baseband Processor

• RAKE Receiver with Decision Feedback Equalizer

• Processing Gain. . . . . . . . . . . . . . . . . . . . FCC Compliant

• Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps

• Ultra Small Package. . . . . . . . . . . . . . . . . . . . . 14 x 14mm

• Single Supply Operation. . . . . . . . . . . . . . . . . 2.7V to 3.6V

• Modulation Methods. . . . . . . . DBPSK, DQPSK, and CCK

• Supports Full or Half Duplex Operations

• On-Chip A/D and D/A Converters for I/Q Data (6-Bit,

22MSPS), AGC, and Adaptive Power Control (7-Bit)

• Targeted for Multipath Delay Spreads 125ns at 11Mbps,

250ns at 5.5Mbps

• Supports Short Preamble and Antenna Diversity

Applications

• PC Card Wireless LAN Adapters

• USB PCMCIA Wireless LAN Adapters

• PCN / Wireless PBX / Wireless Local Loop

• High Data Rate Wireless LAN Systems Targeting IEEE

802.11b Standard

• Wireless LAN Access Points and Bridge Products

• Spread Spectrum WLAN RF Modems

• TDMA or CSMA Packet Protocol Radios

• PCI Wireless LAN Cards (Using Ext. Bridge Chip)

• ISA, ISA PNP WLAN Cards

Ordering Information

PART

NUMBER

TEMP.

RANGE (

C) PACKAGE

PART

NUMBER

ISL3873IK -40 to 85 192 BGA V192.14x14

ISL3873IK96 -40 to 85 Tape and Reel 1000 Units /Reel

Data Sheet February 2001

Microsoft® and Windows® are registered trademarks of Microsoft Corporation.

PRISM® is a registered trademark of Intersil Americas Inc.

PRISM and design is a trademark of Intersil Americas Inc.

Summary of content (31 pages)

PAGE 1
ISL3873 TM Data Sheet February 2001 File Number 4868.2 Wireless LAN Integrated Medium Access Controller with Baseband Processor New Features of the ISL3873 The Intersil ISL3873 Wireless LAN Integrated Medium Access Controller with Integrated Baseband Processor is part of the PRISM® 2.4GHz radio chip set. The ISL3873 directly interfaces with the Intersil’s IF QMODEM (HFA3783).
PAGE 2
ISL3873 Simplified Block Diagram HOST COMPUTER DATA ADDRESS CONTROL USB ISL3873 USB HOST INTERFACE PC CARD HOST INTERFACE ANT_SEL RX_RF_AGC 1 1 AGC CTL MICROPROGRAMMED MAC ENGINE PRISM RADIO RF SECTION THRESH.
PAGE 3
ISL3873 ISL3873 Signal Descriptions HOST INTERFACE PINS PIN NAME PIN I/O TYPE DESCRIPTION HA0-9 5V tol, CMOS, Input, 50K Pull Down Host PC Card Address Input, Bits 0 to 9 HCE1- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Select, Low Byte HCE2- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Select, High Byte HD0-15 5V tol, BiDir, 2mA, 50K Pull Down Host PC Card Data Bus, Bit 0 to 15 HINPACK- CMOS Output, 2mA Host PC Card I/O Decode Confirmation HIORD- 5V tol, CMOS, Input, 50K Pull Up Hos
PAGE 4
ISL3873 MAC RADIO INTERFACE AND GENERAL PURPOSE PORT PINS PIN NAME DESCRIPTION OF FUNCTION (IF OTHER THAN I/O PORT) PIN I/O TYPE PJ4 CMOS BiDir, 2mA PE1 PJ5 CMOS BiDir, 2mA, 50K Pull Up LE_IF PJ6 CMOS BiDir, 2mA LED1 PJ7 CMOS BiDir, 2mA, 50K Pull Up RADIO_PE PK0 CMOS BiDir, 2mA, ST, 50K Pull Down LE_RF PK1 CMOS BiDir, 2mA, 50K Pull Down SYNTHCLK PK2 CMOS BiDir, 2mA, 50K Pull Down SYNTHDATA PK3 CMOS BiDir, 2mA PA_PE PK4 CMOS BiDir, 2mA PE2 PK7 CMOS BiDir, 2mA CAL_EN PL3 CMOS
PAGE 5
ISL3873 MISC CONTROL PORT PINS PIN NAME PIN I/O TYPE DESCRIPTION ANTSEL O The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for differential drive of antenna switches ANTSEL O The antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode.
PAGE 6
ISL3873 ISL3873 PIN NUMBER ASSIGNMENTS (CONTINUED) PIN NUMBER B2 SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME NC D8 HD5 H4 MD13 M16 VDD B3 MA9 D9 HIREQ H13 HD2 B4 MA12 D10 HIOWR H14 HD1 N1 MD4 B5 VDD D11 HOE H15 HA0 N2 MD0 H16 HD8 B6 MA18 D12 NC B7 DBG1 D13 HA5 N3 MD3 N4 MD2 B8 HD12 D14 HWAIT J1 XTALIN N5 NC B9 HCE1 D15 SUPPLY5V J2 XTALOUT N6 PJ7 (RADIO_PE) B10 VDD D16 HREG J3 RAMCS N7 PK2 (SYNTHDAT
PAGE 7
ISL3873 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Typical, Note 1) θJA (oC/W) BGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Storage Temperature Range . . . . . . . . . .
PAGE 8
ISL3873 AC Electrical Specifications (Continued) SYMBOL MIN TYP MAX UNITS SYNTHCLK(PK1) Width Hi PARAMETER tH1 tCYC /2 - 10 - tCYC /2 + 10 ns SYNTHCLK(PK1) Width Lo tL1 tCYC /2 - 10 - tCYC /2 + 10 ns SERIAL PORT SYNTHCLK(PK1) Clock Period tCYC 83ns - 4000 ns tH1 , tL1 tCYC/2 -10 - tCYC/2 + 10 ns tCD - 10 - ns tDRS 15 - - ns Hold Time of SYTHNDATA(PK2) Read from SYTHNCLK(PK1) Falling Edge tDRH 0 - - Hold Time of SYTHNDATA(PK2) Write from SYTHNCLK(PK1) Falling Edge
PAGE 9
ISL3873 Waveforms ADDRESS MA(17..1) tH1 RAMCS_ tH2 tS1 MOE_ tS2 tD1 tE1 MD(15..0) FIGURE 1. EXTERNAL MEMORY READ TIMING ADDRESS MA(17..1) tH3 RAMCS_ tS4 tH4 MWE_ tH5 tS3 MD(15..0) tS5 FIGURE 2. EXTERNAL MEMORY WRITE TIMING SYNTHCLK tH1 SYNLE SPCSPWR tD3 tCYC tD1 SYNTHDATA tL1 tD2 D[n] D[n -1] D[n -2] D[2] FIGURE 3.
PAGE 10
ISL3873 Waveforms (Continued) HA[15:0] tSUREG tHREG HREGISUCE tHCE HCE(1, 2) tWIORD tHA tDIORD HIORDtSUA tDRINPACK tDFINPACK HINPACK- HWAITtWWT tDFWT tDRWT tHIORD HD[15:0] FIGURE 4. PC CARD IO READ 16 HA[15:0] tHREG tSUREG HREGN- tHCE tSUCE HCE (1, 2) tSUA tWIOWR tHA HIOWRtDRINPACK tDRIOWR HWAIT- tDFWT tSUIOWR tWWT HD[15:0] FIGURE 5.
PAGE 11
ISL3873 I ISL3873 MAC System Overview ISL3873 FLASH 128Kx8 MD0..15 MD0..7 MA1..17 MA0..16 NVCS_ CS_ MOE_ OE_ SRAM 128Kx8 SRAM 128Kx8 MD0..7 MA1..17 OE_ MD8..15 MWEL_ WE_ MA1..17 MA0/MWEH_ CS_ OE_ WE_ CS_ RAMCS_ FIGURE 6. 8-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873 FLASH 128Kx16 ISL3873 MA1..17 ADDR(0..16) MD0..15 DATA(0..15) NVCS- CEOE- MA0/MWEH- WE SRAM 128Kx16 ADDR(0..16) DATA(0..15) UBMLBE- LB- RAMCS- CE- MOE- OE MWEL- WE FIGURE 7.
PAGE 12
ISL3873 LARGE SERIAL EEPROM SMALL SERIAL EEPROM PULLUP MISO (PJ2) AO SD (PJ1) SI ISL3873 SCLK (PJ0) ISL3873 SO SCK PULLUP CS# (TCLKIN) SDA SCLK (PJ0) SCL RESET# CS# (TCLKIN) CS 45DB011 A2 WP WP# PULLUP A1 24C08 (NOTE) NOTE: Must operate at 400kHz AT 3.3VDC FIGURE 8. SERIAL EEPROM INTERFACE External Memory Interface The ISL3873 provides separate external chip selects for code space and data storage space.
PAGE 13
ISL3873 For 8-bit spaces, the ISL3873 dynamically configures pin MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB. MWEL-/MWE- is the only write control, and MOE- is the read output enable. HA[9:6] are ignored when the internal HAMASK register is set to the defaults used by the standard firmware. During attribute memory accesses HA[9:1] are used.
PAGE 14
ISL3873 • WAIT will assert until the memory arbitration and access have completed. Note: All register cycles, including hardware registers, incur a short wait state on the PC Card bus to insure the host cycle is synchronized with the ISL3873's internal MCLK. Buffer Access Paths, BAP0 and BAP1 Memory Mapped Registers in Data RAM (MM) • An internal Pre-Read cycle to memory is initiated by a host Buffer Read cycle, after the internal address pointer has auto-incremented.
PAGE 15
ISL3873 FID BUFFER DESCRIPTOR ACCESS (FIRMWARE) ALLOCATE/ DEALLOCATE REQUEST BLOCK BUFFER MEMORY VIRTUAL FRAME BUFFER STATUS A OFFSET CENTER OFFSET HEADER HOST BUS DATA PORT PRE-READ/ POST-WRITE D DATA FIGURE 9. BLOCK DIAGRAM OF A BUFFER ACCESS PATH USB Port The USB interface implemented in the ISL3873 complies with the Universal Serial Bus Specification Revision 1.1. dated September 23, 1998, which is available from the USB Implementers’ Forum at http://www.usb.org/.
PAGE 16
ISL3873 PE1 PE2 TR_SW TR_SW_BAR tD5 tD1 PA_PE tD3 tD4 FIGURE 10. TRANSMIT CONTROL SIGNAL SEQUENCING tuning-fork type watch crystal to permit accurate timekeeping with very low power consumption during sleep state. TABLE 2.
PAGE 17
ISL3873 memory devices at any CLKIN frequency. The MCLK prescaler generates glitch free output when the divisor is changed. This allows firmware to change the MCLK frequency during operation, which is especially useful to selectively reduce operating speed, thereby conserving power, when full speed processing is not required. 22pF XTALIN C1 X1 Option Register (COR, bit 7). RESET originates from the HOST system which applies RESET for at least 0.
PAGE 18
ISL3873 Baseband Processor The Baseband Processor operation is controlled by the ISL3873 firmware. Detailed information on programming the Baseband Processor can be obtain by contacting the factory. BBP Packet Reception The receive demodulator scrutinizes I and Q for packet activity. When a packet arrives at a valid signal level the demodulator acquires and tracks the incoming signal. It then sifts through the demodulator data for the Start Frame Delimiter (SFD).
PAGE 19
ISL3873 Header/Packet Description achieve initial Pseudo Noise (PN) synchronization while the header includes the necessary data fields of the communications protocol to establish the physical layer link. The transmitter generates the synchronization preamble and header and knows when to make the DBPSK to DQPSK or CCK switchover, as required. The ISL3873 is designed to handle packetized Direct Sequence Spread Spectrum (DSSS) data transmissions.
PAGE 20
ISL3873 802.11 DSSS BPSK 1Mbps BARKER 802.11 DSSS QPSK 2Mbps BARKER 5.5Mbps CCK COMPLEX SPREAD FUNCTIONS 11Mbps CCK COMPLEX SPREAD FUNCTIONS DATA 1 BIT ENCODED TO ONE OF 2 CODE WORDS (TRUE-INVERSE) 2 BITS ENCODED TO ONE OF 4 CODE WORDS 4 BITS ENCODED TO ONE OF 16 COMPLEX CCK CODE WORDS 8 BITS ENCODED TO ONE OF 256 COMPLEX CCK CODE WORDS IOUT QOUT CHIP RATE SYMBOL RATE 11 CHIPS 11 CHIPS 8 CHIPS 8 CHIPS 11 MC/S 11 MC/S 11 MC/S 11 MC/S 1 MS/S 1 MS/S 1.375 MS/S 1.375 MS/S I vs.
PAGE 21
ISL3873 CR 3 - Defines the short preamble length minus the SFD in symbols. The 802.11 protocol requires a setting of 56d = 38h for the optional short preamble. CR 4 - Defines the long preamble length minus the SFD in symbols. The 802.11 protocol requires a setting of 128d = 80h for the mandatory long preamble. CR 5 Bits 0, 1 - These bits of the register set the Signal field to indicate what modulation is to be used for the data portion of the packet. CR 6 - The value to be used in the Service field.
PAGE 22
ISL3873 CCK symbol. All odd numbered symbols of the MPDU are given an extra 180 degree (π) rotation in accordance with the DQPSK modulation as shown in Table 8. Symbol numbering starts with “0” for the first symbol of the MPDU. (LSB to MSB), where c is the code word. The terms: ϕ1, ϕ2, ϕ3, and ϕ4 are defined below for 5.5Mbps and 11Mbps. This formula creates 8 complex chips (LSB to MSB) that are transmitted LSB first.
PAGE 23
ISL3873 various internal parameters (i.e., Energy Detection measurement results), can assist the MAC in executing algorithms that can adapt to the environment. These algorithms can increase network throughput by minimizing collisions and reducing transmissions liable to errors. There are three measures that can be used in the CCA assessment. The Receive Signal Strength Indication (RSSI) which indicates the energy at the antenna, CS1 and carrier sense (SQ1).
PAGE 24
ISL3873 RX_RF_AGC Pad Operation 30dB Pad Engaging (RF Chip Low Gain): If the AGC is not locked onto a packet, a '1' on the ifCompDet input will engage in the 30dB attenuation pad. This causes the AGC to go out of lock and also forces the attenuation accumulator to be set to the programmed value of CR27. The AGC then attempts to lock on the signal. If the AGC is locked on a packet, ifCompDet is ignored.
PAGE 25
ISL3873 TX POWER RAMP SFD 56 SYMBOL SYNC 2 20 SYMBOLS 20 SYMBOLS 7 SYM AGC SETTLE AND LOCK AND INITIAL DETECTION VERIFY AND CIR/FREQUENCY ESTIMATION AND CMF/NCO JAMMING 16 SYMBOLS SFD DET START DATA SEED DESCRAMBLER START SFD SEARCH FIGURE 16.
PAGE 26
ISL3873 Channel Matched Filter (CMF) Description The receive section shown in Figure 19 operates on the RAKE receiver principle which maximizes the SNR of the signal by combining the energy of multipath signal components. The RAKE receiver is implemented with a Channel Matched Filter (CMF) using a FIR filter structure with 16 taps. The CMF is programmed by calculating the Channel Impulse Response (CIR) of the channel and mathematically manipulating that to form the tap coefficients of the CMF.
PAGE 27
ISL3873 SAMPLES AT 2X CHIP RATE CORRELATION PEAK CORRELATION TIME T0 + 1 SYMBOL CORRELATOR T0 OUTPUT REPEATS CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PSEUDO NOISE(PN) SEQUENCE WITH THE RECEIVED SIGNAL EARLY ON-TIME LATE T0 + 2 SYMBOLS FIGURE 18. CORRELATION PROCESS Data Demodulation in the CCK Modes In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two highest data rates.
PAGE 28
ISL3873 VDDA (ANALOG) GND (ANALOG) VDD (DIGITAL) GND (DIGITAL) CCA to MAC (INTERNAL) RX_IF_DET RX_IF_AGC 6 6-BIT A/D 6 CORRELATOR BARKER 6-BIT A/D BIT SYNC 8 PEAK EXTRACT. 8 RXD TO MAC EQUAL. BIAS ADDER SYMBOL DECISION MUX MUX RECEIVE STATE MACHINE ANTENNA SWITCH CONTROL TIMING GENERATOR MCLK RESET RX_PE MCLK FIGURE 19.
PAGE 29
ISL3873 This section indicates the typical performance measures for a radio design. The performance data below should be used as a guide. In general, the actual performance depends on the application, interference environment, RF/IF implementation and radio component selection. the link do not have locked oscillators, then symbol tracking is done by a conventional early-late chip tracking method. Eb/N0 7 8 9 10 11 12 1.E-01 Overall Eb/N0 Versus BER Performance 1.E-02 BER 2.
PAGE 30
ISL3873 RSSI Performance 100 The RSSI value is reported on CR62 in hex and is linear with signal level in dB. Figure 22 shows the RSSI curve measured on a whole evaluation radio. This takes into account the full gain adjust range of all radio parts. To get signal level in dBm on a radio, simply subtract the RSSI value in decimal from 100. 120 RSSI 100 90 80 70 60 50 40 PER 30 MEAN 20 STDDEV 10 0 -10 RSSI IN DE 80 -5 0 5 10 15 20 25 SNR IN THE SPREAD BANDWIDTH AT 1Mbps FIGURE 23.
PAGE 31
ISL3873 Plastic Ball Grid Array Packages (BGA) o A1 CORNER A D V192.14x14 192 BALL PLASTIC BALL GRID ARRAY PACKAGE A1 CORNER I.D. INCHES E B TOP VIEW 0.15 M C A B 0.006 0.08 M C 0.003 b A1 CORNER D1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A1 CORNER I.D. A B C D E F G H E1 J K L M N P R T S A SYMBOL MIN MAX MIN MAX NOTES A - 0.059 - 1.40 - A1 0.012 0.016 0.31 0.41 - A2 0.033 0.039 0.83 0.99 - b 0.016 0.020 0.41 0.51 7 D/E 0.547 0.555 13.90 14.10 - D1/E1 0.