CC1100E Low-Power Sub-GHz RF Transceiver (470-510 MHz & 950-960 MHz) Applications Ultra low-power wireless applications operating in the 470/950 MHz ISM/SRD bands Wireless sensor networks Home and building automation Advanced Metering Infrastructure (AMI) Wireless metering Wireless alarm and security systems Product Description The CC1100E is a Sub-GHz high performance radio transceiver designed for very low power RF applications.
CC1100E Key Features RF Performance High sensitivity (–112 dBm at 1.2 kBaud, 480 MHz, 1% packet error rate) Low current consumption (15.5 mA in RX, 1.2 kBaud, 480 MHz) Programmable output power up to +10 dBm for all supported frequencies Excellent receiver selectivity and blocking performance Programmable data rate from 1.
CC1100E Abbreviations Abbreviations used in this data sheet are described below.
CC1100E Table of Contents APPLICATIONS .................................................................................................................................................. 1 PRODUCT DESCRIPTION................................................................................................................................ 1 KEY FEATURES .................................................................................................................................................
CC1100E 14 14.1 14.2 14.3 15 15.1 15.2 15.3 15.4 15.5 15.6 16 16.1 16.2 16.3 17 17.1 17.2 17.3 17.4 17.5 17.6 18 18.1 18.2 19 19.1 19.2 19.3 19.4 19.5 19.6 19.7 20 21 22 22.1 23 24 25 26 27 27.1 27.2 28 28.1 28.2 28.3 28.4 28.5 28.6 28.7 29 29.1 29.2 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION.................................. 32 FREQUENCY OFFSET COMPENSATION........................................................................................................ 32 BIT SYNCHRONIZATION ..............
CC1100E 29.3 STATUS REGISTER DETAILS....................................................................................................................... 85 30 PACKAGE DESCRIPTION (QFN 20)................................................................................................. 89 30.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QFN 20)........................................................................... 89 30.2 SOLDERING INFORMATION ...................................................................
CC1100E 1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Min Max Units Supply voltage –0.3 3.9 V Voltage on any digital pin –0.3 VDD + 0.3 Condition All supply pins must have the same voltage max 3.9 V 2.
CC1100E 4 Electrical Specifications 4.1 Current Consumption TA = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1100E EM reference designs ([3] and[4]). Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Table 6: RF Receive Section for additional details on current consumption and sensitivity.
CC1100E Parameter Min Current consumption, 955 MHz Typ Max Unit Condition 16.3 mA Receive mode, 1.2 kBaud , reduced current, input at sensitivity limit 15.2 mA Receive mode, 1.2 kBaud , reduced current, input well above sensitivity limit 17.7 mA Receive mode, 38.4 kBaud , reduced current, input at sensitivity limit 17.0 mA Receive mode, 38.4 kBaud , reduced current, input well above sensitivity limit 16.8 mA Receive mode, 76.8 kBaud , reduced current, input at sensitivity limit 15.
CC1100E 4.2 RF Receive Section TA = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1100E EM reference designs ([3] and[4]). Parameter Digital channel filter bandwidth Min Typ 58 Max Unit Condition/Note 812 kHz User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal) 480 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.
CC1100E TA = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1100E EM reference designs ([3] and[4]) 955 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK with BT=1, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity -104 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1.
CC1100E Supply VDD = 1.8 V Voltage Supply VDD = 3.0 V Voltage Supply VDD = 3.6 V Voltage Temperature [°C] -40 25 85 -40 25 85 -40 25 85 Sensitivity [dBm] -101 -100 -96 -102 -100 -98 -102 -100 -98 Table 7: Typical Variation in Sensitivity over Temperature and Supply Voltage, 955 MHz, 76.8 kBaud GFSK, Sensitivity Optimized Setting, 770 MHz notch filter Used 60.0 50.0 Selectivity [dB] 40.0 30.0 20.0 10.0 0.0 -10.0 -20.0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.
CC1100E 4.3 RF Transmit Section TA = 25C, VDD = 3.0 V, +10dBm if nothing else stated. All measurement results are obtained using the CC1100E EM reference designs ([3] and[4]). Parameter Min Typ Max Unit Differential load impedance 480 MHz 132 – j2 955 MHz 59 – j67 Output power, highest setting Condition/Note Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna.
CC1100E Supply Voltage VDD = 1.8 V Supply Voltage VDD = 3.0 V Supply Voltage VDD = 3.6 V Temperature [°C] -40 25 85 -40 25 85 -40 25 85 Output Power [dBm] 10.1 10.8 10.8 10.2 10.4 10.5 9.2 9.9 9.9 Table 9: Typical Variation in Output Power over Temperature and Supply Voltage, 480 MHz, +10 dBm Output Power Setting Supply Voltage VDD = 1.8 V Supply Voltage VDD = 3.0 V Supply Voltage VDD = 3.6 V Temperature [°C] -40 25 85 -40 25 85 -40 25 85 Output Power [dBm] 8.8 8.4 7.
CC1100E 4.6 Frequency Synthesizer Characteristics TA = 25C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1100E EM reference designs ([3] and[4]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal. Parameter Programmed frequency resolution Min Typ 397 Max FXOSC/ 216 Unit 412 Condition/Note Hz 26-27 MHz crystal. The resolution (in Hz) is equal for all frequency bands Given by crystal used.
CC1100E 4.8 DC Characteristics TA = 25C if nothing else stated. Digital Inputs/Outputs Min Max Unit Condition Logic "0" input voltage 0 0.7 V Logic "1" input voltage VDD-0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 mA output current Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current Logic "0" input current N/A –50 nA Input equals 0V Logic "1" input current N/A 50 nA Input equals VDD Table 15: DC Characteristics 4.
CC1100E Pin # Pin Name Pin type Description 1 SCLK Digital Input Serial configuration interface, clock input 2 SO (GDO1) Digital Output Serial configuration interface, data output Optional general output pin when CSn is high 3 GDO2 Digital Output Digital output pin for general use: Test signals FIFO status signals Clear channel indicator Clock output, down-divided from XOSC Serial output RX data 4 DVDD Power (Digital) 1.8 - 3.
CC1100E 6 Circuit Description 90 PA RC OSC BIAS RBIAS XOSC XOSC_Q1 RXFIFO DIGITAL INTERFACE TO MCU 0 RF_N TXFIFO FREQ SYNTH MODULATOR RF_P PACKET HANDLER ADC FEC / INTERLEAVER ADC LNA DEMODULATOR RADIO CONTROL SCLK SO (GDO1) SI CSn GDO0 (ATEST) GDO2 XOSC_Q2 Figure 5: CC1100E Simplified Block Diagram A simplified block diagram of the CC1100E is shown in Figure 5. The CC1100E features a low-IF receiver.
CC1100E signals are joined together (C131, C121, L121 and L131 for the 470 MHz reference design [3], and L121, L131, C121, L122, C131, C122 and L132 for the 950 MHz reference design [4]) form a balun that converts the differential RF signal on the CC1100E to a single-ended RF signal. C124 is needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50 load. C125 provides DC blocking and is only needed if there is a DC path in the antenna.
CC1100E 7.7 Antenna Considerations The reference designs ([3] and 0) contain an SMA connector and are matched for a 50 load. The SMA connector makes it easy to connect evaluation modules and prototypes to different test equipment for example a Component C51 spectrum analyzer. The SMA connector can also be replaced by an antenna suitable for the desired application. Please refer to the antenna selection guide [14] for further details regarding antenna solutions provided by TI.
CC1100E 1.8V-3.
CC1100E Component Value at 470MHz Value at 950MHz Manufacturer C51 100 nF ± 10%, 0402 X5R Murata GRM1555C series C81 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C101 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C121 3.9 pF ± 0.25 pF, 0402 NP0 1.0 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C122 6.8 pF ± 5% pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C123 5.6 pF ± 0.5 pF, 0402 NP0 2.7 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C124 .
CC1100E 100%. See Figure 8 for top solder resist and top paste masks. Each decoupling capacitor should be placed as close as possible to the supply pin it decouples. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC1100E supply pin. Supply power filtering is very important.
CC1100E Sleep SPWD or wake-on-radio (WOR) SIDLE Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.7 mA. CSn = 0 Lowest power mode. Most register values are retained. Current consumption typ 300 nA, or typ 700 nA when wake-on-radio (WOR) is enabled. IDLE SXOFF SCAL Used for calibrating frequency synthesizer upfront (entering CSn = 0 receive or transmit mode can Manual freq. then be done quicker). synth.
CC1100E 9 Configuration Software The CC1100E can be configured using the SmartRF Studio software [8]. The SmartRF Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF Studio user interface for the CC1100E is shown in Figure 10. After chip reset, all the registers have default values as shown in the tables in Section 29. The optimum register setting might differ from the default value.
CC1100E tsp tch tcl tsd thd tns SCLK: CSn: Write to register: SI X 0 B A5 SO Hi-Z S7 B S5 SI X A4 A3 A2 A1 A0 S4 S3 S2 S1 S0 X DW7 DW 6 S6 S7 DW5 S5 DW4 DW 3 DW2 DW1 DW0 S3 S2 S1 S0 DR2 DR1 S4 X Hi-Z Read from register: SO Hi-Z 1 B A5 A4 A3 A2 A1 A0 S7 B S5 S4 S3 S2 S1 S0 X DR7 DR6 DR5 DR4 DR3 DR0 Hi-Z Figure 11: Configuration Registers Write and Read Operations Parameter Description Min Max Units fSCLK SCLK frequency - 10 MHz
CC1100E 10.1 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC1100E on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running. Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip.
CC1100E burst bit (B) in the header byte. The address bits (A5 – A0) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high. status registers when burst bit is one, and between command strobes when burst bit is zero. See more in Section 10.3 below.
CC1100E expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO.
CC1100E 11 Microcontroller Interface and Pin Configuration In a typical system, the CC1100E will interface to a microcontroller. This microcontroller must be able to: Program the CC1100E into different modes Read and write buffered data Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn) 11.1 Configuration Interface The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn).
CC1100E 12 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.
CC1100E 14 Demodulator, Symbol Synchronizer, and Data Decision The CC1100E contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 17.3 for more information), the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 14.1 Frequency Offset Compensation The CC1100E has a very fine frequency resolution (see Table 13).
CC1100E 15 Packet Handling Hardware Support The CC1100E has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO: A programmable number of preamble bytes A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word A CRC checksum computed over the data field.
CC1100E Figure 14: Data Whitening in TX Mode 15.2 Packet Format The format of the data packet can be configured and consists of the following items (see Figure 15): Preamble Synchronization word Optional length byte Optional address byte Payload Optional 2 byte CRC Data field 16/32 bits 8 bits 8 bits 8 x n bits Legend: Inserted automatically in TX, processed and removed in RX. CRC-16 Address field 8 x n bits Length field Preamble bits (1010...
CC1100E packets, infinite packet length mode must be used. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional CRC. The PKTLEN register is used to set the maximum packet length allowed in RX.
CC1100E Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again 0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,....................... Infinite packet length enabled Fixed packet length enabled when less than 256 bytes remains of packet 600 bytes transmitted and received Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88 Figure 16: Packet Length > 255 15.
CC1100E The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state.
CC1100E It is recommended to employ an interrupt driven solution since high rate SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 10.3 and the CC1100E Errata Note [5], when using SPI polling, there is a small, but finite, probability that a single read from registers PKTSTATUS , RXBYTES and TXBYTES is being corrupt. The same is the case when reading the chip status byte. Refer to the TI website for SW examples ([9] and [10]).
CC1100E 16.3 Amplitude Modulation The CC1100E supports two different forms of amplitude modulation: On-Off Keying (OOK) and Amplitude Shift Keying (ASK). OOK modulation simply turns the PA on or off to modulate ones and zeros respectively. The ASK variant supported by the CC1100E allows programming of the modulation depth (the difference between 1 and 0), and shaping of the pulse amplitude. Pulse shaping produces a more output spectrum.
CC1100E 17.3 RSSI The RSSI value is an estimate of the signal power level in the chosen channel. This value is based on the current gain setting in the RX chain and the measured signal level in the channel. In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen until the next time the chip enters the RX state.
CC1100E 0 -10 -20 RSSI Readout (dBm) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power (dBm) 1.2 kBaud 38.4 kBaud 250 kBaud Figure 17: Typical RSSI Value vs. Input Power Level for Different Data Rates at 480 MHz 0.00 -10.00 -20.00 RSSI Readout (dBm) -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 -110.00 -120.00 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power (dBm) 1.2 kBaud 38.4 kBaud 76.
CC1100E level and is thus useful to detect signals in environments with time varying noise floor. See more in Section 17.4.2. Other uses of Carrier sense include the TX-ifCCA function (see Section 17.5 on page 43) and the optional fast RX termination (see Section 19.7 on page 49). CS can be used to avoid interference from other RF sources in the ISM bands.
CC1100E 17.5 Clear Channel Assessment (CCA) The Clear Channel Assessment (CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on any of the GDO pins by setting IOCFGx.GDOx_CFG=0x09. not enter TX or FSTXON state before a new strobe command is sent on the SPI interface. This feature is called TX-if-CCA. Four CCA requirements can be programmed: Always (CCA disabled, always goes to TX) MCSM1.CCA_MODE selects the mode to use when determining CCA.
CC1100E 18.2 Interleaving Data received through radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. passed onto the convolutional decoder is read from the columns of the matrix.
CC1100E 19 Radio Control SIDLE SPWD | SWOR SLEEP 0 CAL_COMPLETE MANCAL 3,4,5 IDLE 1 CSn = 0 | WOR SXOFF SCAL CSn = 0 XOFF 2 SRX | STX | SFSTXON | WOR FS_WAKEUP 6,7 FS_AUTOCAL = 01 & SRX | STX | SFSTXON | WOR FS_AUTOCAL = 00 | 10 | 11 & SRX | STX | SFSTXON | WOR SETTLING 9,10,11 SFSTXON CALIBRATE 8 CAL_COMPLETE FSTXON 18 STX SRX STX TXOFF_MODE=01 SFSTXON | RXOFF_MODE = 01 STX | RXOFF_MODE = 10 TXOFF_MODE = 10 SRX | WOR RXTX_SETTLING 21 TX 19,20 SRX | TXOFF_MODE = 11 TXOFF_MODE = 00 &
CC1100E signal with a frequency of CLK_XOSC/192. However, to optimize performance in TX and RX, an alternative GDO setting from the settings found in Table 36 on page 55 should be selected. manual power-up sequence is as follows (see Figure 22): Set SCLK = 1 and SI = 0, to avoid potential problems with pin control mode (see Section 11.3 on page 30). 19.1.1 Automatic POR Strobe CSn low / high. A power-on reset circuit is included in the CC1100E.
CC1100E 19.3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.
CC1100E 19.5 Wake On Radio (WOR) The optional Wake on Radio (WOR) functionality enables the CC1100E to periodically wake up from SLEEP and listen for incoming packets without MCU interaction. When the SWOR strobe command is sent on the SPI interface, the CC1100E will go to the SLEEP state when CSn is released. The RC oscillator must be enabled before the SWOR strobe can be used, as it is the clock source for the WOR timer. The on-chip timer will set the CC1100E into IDLE state and then RX state.
CC1100E RC oscillator calibration is turned off, it will have to be manually turned on again if the temperature and/or the supply voltage changes. Refer to Application Note AN047 [7] for further details. 19.6 Timing The radio controller controls most of the timing in the CC1100E, such as synthesizer calibration, PLL lock time, and RX/TX turnaround times. Timing from IDLE to RX and IDLE to TX is constant, dependent on the auto calibration setting. RX/TX and TX/RX turnaround times are constant.
CC1100E 20 Data FIFO The CC1100E contains two 64 byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO. Section 10.5 contains details on the SPI FIFO access. The FIFO controller will detect overflow in the RX FIFO and underflow in the TX FIFO. When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflow will result in an error in the TX FIFO content.
CC1100E Figure 24 Example of FIFOs at Threshold Overflow margin FIFO_THR=13 NUM_RXBYTES 53 54 55 56 57 56 55 54 53 GDO 56 bytes NUM_TXBYTES 6 7 8 9 10 9 8 7 6 GDO Figure 25: Number of Bytes in FIFO vs. the GDO Signal (GDOx_CFG=0x00 in RX and GDOx_CFG=0x02 in TX, FIFO_THR=13) FIFO_THR=13 Underflow margin 8 bytes RXFIFO TXFIFO 21 Frequency Programming The frequency programming in the CC1100E is designed to minimize the programming needed in a channel-oriented system.
CC1100E 22 VCO The VCO is completely integrated on-chip. 22.1 VCO and PLL Self-Calibration The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, the CC1100E includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel).
CC1100E If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively. See Section 10.6 on page 29 for PATABLE programming details. PATABLE must be programmed in burst mode if you want to write to other entries than PATABLE[0]. Table 33 contains recommended PATABLE settings for various output levels and frequency bands. DN013 Error! Reference source not found. gives the complete tables for the different frequency bands.
CC1100E shows some examples of ASK shaping. configuration of the PATABLE. Figure 27 PATABLE(7)[7:0] PATABLE(6)[7:0] The PA uses this setting. PATABLE(5)[7:0] PATABLE(4)[7:0] PATABLE(3)[7:0] PATABLE(2)[7:0] PATABLE(1)[7:0] Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for ASK/OOK modulation. PATABLE(0)[7:0] Index into PATABLE(7:0) e.
CC1100E GDOx_CFG[5:0] 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) 16 (0x10) 17 (0x11) 18 (0x12) 19 (0x13) 20 (0x14) 21 (0x15) 22 (0x16) 23 (0x17) 24 (0x18) 25 (0x19) 26 (0x1A) 27 (0x1B) 28 (0x1C) 29 (0x1D) 30 (0x1E) 31 (0x1F) 32 (0x20) 33 (0x21) 34 (0x22) 35 (0x23) 36 (0x24) 37 (0x25) 38 (0x26) 39 (0x27) 40 (0x28) 41 (0x29) 42 (0x2A) 43 (0x2B) 44 (0x2C) 45 (0x2D) 46 (0x2E) 47 (0x2F) 48 (0x30) 49 (0x31)
CC1100E 27 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC1100E to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, significantly offload the microcontroller, and simplify software development. 27.
CC1100E 28 System Considerations and Guidelines 28.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. The CC1100E is specifically designed for use in the license free 470-510 MHz and 950-960 MHz frequency bands in China and Japan, respectively. with two and three unit channels.
CC1100E The CC1100E is highly suited for FHSS or multichannel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller. Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for the CC1100E.
CC1100E 28.5 Low Cost Systems As the CC1100E provides 1.2 - 500 kBaud multichannel performance without any external SAW or loop filters, a very low cost system can be made. The crystal package strongly influences the price. In a size constrained PCB design, a smaller, but more expensive, crystal may be used. A HC-49 type SMD crystal is used in the CC1100E EM reference designs ([3] and 0). 28.
CC1100E Table 41 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F. Address Strobe Name Description 0x30 SRES Reset chip. 0x31 SFSTXON 0x32 SXOFF 0x33 SCAL Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.
CC1100E Preserved in SLEEP State Details on Page Number GDO2 output pin configuration GDO1 output pin configuration GDO0 output pin configuration Yes 64 Yes 64 Yes 64 RX FIFO and TX FIFO thresholds Yes 65 Address Register Description 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 Sync word, high byte Yes 66 0x05 SYNC0 Sync word, low byte Yes 66 0x06 PKTLEN Packet length Yes 66 0x07 PKTCTRL1 Packet automation control Yes 66 0x08 PKTCTRL0 Packet automa
CC1100E Address Register Description Details on page number 0x30 (0xF0) PARTNUM Part number for the CC1100E 85 0x31 (0xF1) VERSION Current version number 85 0x32 (0xF2) FREQEST Frequency Offset Estimate 85 0x33 (0xF3) LQI Demodulator estimate for Link Quality 85 0x34 (0xF4) RSSI Received signal strength indication 85 0x35 (0xF5) MARCSTATE Control state machine state 86 0x36 (0xF6) WORTIME1 High byte of WOR timer 86 0x37 (0xF7) WORTIME0 Low byte of WOR timer 86 0x38 (0xF8)
CC1100E SRES SFSTXON SXOFF SCAL SRX STX SIDLE SRES SFSTXON SXOFF SCAL SRX STX SIDLE SWOR SPWD SFRX SFTX SWORRST SNOP PATABLE TX FIFO SWOR SPWD SFRX SFTX SWORRST SNOP PATABLE RX FIFO PATABLE TX FIFO Burst +0xC0 R/W configuration registers, burst access possible 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x3
CC1100E 29.1 Configuration Register Details – Registers with preserved values in SLEEP state 0x00: IOCFG2 – GDO2 Output Pin Configuration Bit Field Name Reset 7 R/W Description R0 Not used 6 GDO2_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO2_CFG[5:0] 41 (0x29) R/W Default is CHP_RDYn (See Table 36 on page 55).
CC1100E 0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds Bit Field Name 7 6 ADC_RETENTION Reset R/W Description 0 R/W Reserved , write 0 for compatibility with possible future extensions 0 R/W 0: TEST1 = 0x31 and TEST2= 0x88 when waking up from SLEEP 1: TEST1 = 0x35 and TEST2 = 0x81 when waking up from SLEEP Note that the changes in the TEST registers due to the ADC_RETENTION bit setting are only seen INTERNALLY in the analog part.
CC1100E 0x04: SYNC1 – Sync Word, High Byte Bit Field Name Reset R/W Description 7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word 0x05: SYNC0 – Sync Word, Low Byte Bit Field Name Reset R/W Description 7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word 0x06: PKTLEN – Packet Length Bit Field Name Reset R/W Description 7:0 PACKET_LENGTH 255 (0xFF) R/W Indicates the packet length when fixed packet length mode is enabled.
CC1100E 0x08: PKTCTRL0 – Packet Automation Control Bit Field Name Reset 7 6 WHITE_DATA 1 R/W Description R0 Not used R/W Turn data whitening on / off 0: Whitening off 1: Whitening on 5:4 PKT_FORMAT[1:0] 3 2 CRC_EN 0 (00) R/W Format of RX and TX data Setting Packet format 0 (00) Normal mode, use FIFOs for RX and TX 1 (01) Synchronous serial mode, Data in on GDO0 and data out on either of the GDOx pins 2 (10) Random TX mode; sends random data using PN9 generator. Used for test.
CC1100E 0x0B: FSCTRL1 – Frequency Synthesizer Control Bit Field Name Reset R/W Description R0 Not used 0 R/W Reserved 15 (0x0F) R/W The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. 7:6 5 4:0 FREQ_IF[4:0] f IF f XOSC FREQ _ IF 210 The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz crystal.
CC1100E 0x10: MDMCFG4 – Modem Configuration Bit Field Name Reset R/W 7:6 CHANBW_E[1:0] 2 (0x02) R/W 5:4 CHANBW_M[1:0] 0 (0x00) R/W Description Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. BWchannel f XOSC 8 (4 CHANBW _ M )·2 CHANBW _ E The default values give 203 kHz channel filter bandwidth, assuming a 26.0 MHz crystal.
CC1100E 0x12: MDMCFG2 – Modem Configuration Bit Field Name Reset R/W Description 7 DEM_DCFILT_OFF 0 R/W Disable digital DC blocking filter before demodulator. 0 = Enable (better sensitivity) 1 = Disable (current optimized). Only for data rates ≤ 250 kBaud The recommended IF frequency changes when the DC blocking is disabled. Please use SmartRF Studio [8] to calculate correct register setting.
CC1100E 0x13: MDMCFG1– Modem Configuration Bit Field Name Reset R/W Description 7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for packet payload 0 = Disable 1 = Enable (Only supported for fixed packet length mode, i.e. PKTCTRL0.
CC1100E 0x15: DEVIATN – Modem Deviation Setting Bit Field Name Reset 7 6:4 DEVIATION_E[2:0] 4 (100) 3 2:0 DEVIATION_M[2:0] 7 (111) R/W Description R0 Not used. R/W Deviation exponent. R0 Not used. R/W TX Specifies the nominal frequency deviation from the carrier for a ‘0’ (-DEVIATN) and ‘1’ (+DEVIATN) in a mantissa-exponent format, interpreted as a 4-bit value with MSB implicit 1.
CC1100E 0x16: MCSM2 – Main Radio Control State Machine Configuration Bit Field Name Reset 7:5 R/W Description R0 Not used 4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carrier sense). For ASK/OOK modulation, RX times out if there is no carrier sense in the first 8 symbol periods. 3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires, the chip checks if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQI is set when RX_TIME_QUAL=1.
CC1100E 0x17: MCSM1– Main Radio Control State Machine Configuration Bit Field Name Reset 7:6 5:4 3:2 CCA_MODE[1:0] RXOFF_MODE[1:0] 3 (11) 0 (00) R/W Description R0 Not used R/W Selects CCA_MODE; Reflected in CCA signal R/W Setting Clear channel indication 0 (00) Always 1 (01) If RSSI below threshold 2 (10) Unless currently receiving a packet 3 (11) If RSSI below threshold unless currently receiving a packet Select what should happen when a packet has been received Setting Next sta
CC1100E 0x18: MCSM0– Main Radio Control State Machine Configuration Bit Field Name Reset 7:6 5:4 FS_AUTOCAL[1:0] 0 (00) R/W Description R0 Not used R/W Automatically calibrate when going to RX or TX, or back to IDLE Setting When to perform automatic calibration 0 (00) Never (manually calibrate using SCAL strobe) 1 (01) When going from IDLE to RX or TX (or FSTXON) 2 (10) When going from RX or TX back to IDLE automatically 3 (11) Every 4th time when going from RX or TX to IDLE automaticall
CC1100E 0x19: FOCCFG – Frequency Offset Compensation Configuration Bit Field Name Reset 7:6 R/W Description R0 Not used 5 FOC_BS_CS_GATE 1 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CS signal goes high. 4:3 FOC_PRE_K[1:0] 2 (10) R/W The frequency compensation loop gain to be used before a sync word is detected. 2 1:0 FOC_POST_K FOC_LIMIT[1:0] 1 2 (10) R/W R/W Setting Freq.
CC1100E 0x1A: BSCFG – Bit Synchronization Configuration Bit Field Name Reset R/W Description 7:6 BS_PRE_KI[1:0] 1 (01) R/W The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): 5:4 3 2 1:0 BS_PRE_KP[1:0] BS_POST_KI BS_POST_KP BS_LIMIT[1:0] 2 (10) 1 1 0 (00) R/W R/W R/W R/W Setting Clock recovery loop integral gain before sync word 0 (00) KI 1 (01) 2KI 2 (10) 3KI 3 (11) 4KI The clock recovery feedba
CC1100E 0x1B: AGCCTRL2 – AGC Control Bit Field Name Reset R/W Description 7:6 MAX_DVGA_GAIN[1:0] 0 (00) R/W Reduces the maximum allowable DVGA gain.
CC1100E 0x1C: AGCCTRL1 – AGC Control Bit Field Name Reset 7 R/W Description R0 Not used 6 AGC_LNA_PRIORITY 1 R/W Selects between two different strategies for LNA and LNA 2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA 2 gain is decreased to minimum before decreasing LNA gain.
CC1100E 0x1D: AGCCTRL0 – AGC Control Bit Field Name Reset R/W Description 7:6 HYST_LEVEL[1:0] 2 (10) R/W Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determine gain changes).
CC1100E 0x1F: WOREVT0 –Low Byte Event0 Timeout Bit Field Name Reset R/W Description 7:0 EVENT0[7:0] 107 (0x6B) R/W Low byte of EVENT0 timeout register. The default EVENT0 value gives 1.0s timeout, assuming a 26.0 MHz crystal. 0x20: WORCTRL – Wake On Radio Control Bit Field Name Reset R/W Description 7 RC_PD 1 R/W Power down signal to RC oscillator. When written to 0, automatic initial calibration will be performed 6:4 EVENT1[2:0] 7 (111) R/W Timeout setting from register block.
CC1100E 0x21: FREND1 – Front End RX Configuration Bit Field Name Reset R/W Description 7:6 LNA_CURRENT[1:0] 1 (01) R/W Adjusts front-end LNA PTAT current output 5:4 LNA2MIX_CURRENT[1:0] 1 (01) R/W Adjusts front-end PTAT outputs 3:2 LODIV_BUF_CURRENT_RX[1:0] 1 (01) R/W Adjusts current in RX LO buffer (LO input to mixer) 1:0 MIX_CURRENT[1:0] 2 (10) R/W Adjusts current in mixer 0x22: FREND0 – Front End TX Configuration Bit Field Name Reset 7:6 5:4 LODIV_BUF_CURRENT_TX[1:0] 1 (0x01
CC1100E 0x24: FSCAL2 – Frequency Synthesizer Calibration Bit Field Name Reset 7:6 R/W Description R0 Not used 5 VCO_CORE_H_EN 0 R/W Choose high (1) / low (0) VCO 4:0 FSCAL2[4:0] 10 (0x0A) R/W Frequency synthesizer calibration results register. VCO current calibration result and override value. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values.
CC1100E 29.2 Configuration Register Details – Registers that Loose Programming in SLEEP State 0x29: FSTEST – Frequency Synthesizer Calibration Control Bit Field Name Reset R/W Description 7:0 FSTEST[7:0] 89 (0x59) R/W For test only. Do not write to this register. 0x2A: PTEST – Production Test Bit Field Name Reset R/W Description 7:0 PTEST[7:0] 127 (0x7F) R/W Writing 0xBF to this register makes the on-chip temperature sensor available in the IDLE state.
CC1100E 0x2E: TEST0 – Various Test Settings Bit Field Name Reset R/W Description 7:2 TEST0[7:2] 2 (0x02) R/W The value to use in this register is given by the SmartRF Studio software [8]. 1 VCO_SEL_CAL_EN 1 R/W Enable VCO selection calibration stage when 1 0 TEST0[0] 1 R/W The value to use in this register is given by the SmartRF Studio software [8]. 29.
CC1100E 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State Bit Field Name Reset 7:5 4:0 MARC_STATE[4:0] R/W Description R0 Not used R Main Radio Control FSM State Value State name State (Figure 20, page 45) 0 (0x00) SLEEP SLEEP 1 (0x01) IDLE IDLE 2 (0x02) XOFF XOFF 3 (0x03) VCOON_MC MANCAL 4 (0x04) REGON_MC MANCAL 5 (0x05) MANCAL MANCAL 6 (0x06) VCOON FS_WAKEUP 7 (0x07) REGON FS_WAKEUP 8 (0x08) STARTCAL CALIBRATE 9 (0x09) BWBOOST SETTLING 10 (0x0A) FS
CC1100E 0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status Bit Field Name 7 Reset R/W Description CRC_OK R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6 CS R Carrier sense 5 PQT_REACHED R Preamble Quality reached 4 CCA R Channel is clear 3 SFD R Sync word found. Asserted when sync word has been sent / received, and de-asserted at the end of the packet.
CC1100E 0x3D (0xFD): RCCTRL0_STATUS – Last RC Oscillator Calibration Result Bit Field Name 7 6:0 RCCTRL0_STATUS[6:0] Reset R/W Description R0 Not used R Contains the value from the last run of the RC oscillator calibration routine. For usage description refer to Application Note AN047 [7].
CC1100E 30 Package Description (QFN 20) 30.1 Recommended PCB Layout for Package (QFN 20) Figure 29: Recommended PCB Layout for QFN 20 Package Note: Figure 29 is an illustration only and not to scale. There are five 10 mil via holes distributed symmetrically in the ground pad under the package. See also the CC1100EEM reference designs ([3] and [4]). 30.2 Soldering Information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed.
CC1100E 30.
CC1100E References [1] CC1101 Datasheet [2] CC1100 Datasheet [3] CC1100E EM 470 MHz Reference Design [4] CC1100E EM 950 MHz Reference Design [5] CC1100E Errata Note [6] ARIB STD-T96 ver.1.0 [7] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf) [8] SmartRF Studio (swrc046.zip) [9] CC1100 CC1101 CC1100E CC2500 Examples Libraries (swrc021.zip) [10] CC1100/CC1150DK, CC1101DK, and CC2500/CC2550DK Examples and Libraries User Manual (swru109.
CC1100E 31 General Information 31.
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