Specifications

Bluegiga Technologies Oy
Page 23 of 64
LDO
(1.8V...3.6V)
EN
IN
VDD_BAT
VREG_ENA
VDD_IO
On/Off cntrl
Battery Voltage
(2.7V...4.4V)
LDO
(1.8V...3.6V)
EN
IN
VDD_BAT
VREG_ENA
VDD_IO
On/Off cntrl
Battery Voltage
(2.7V...4.4V)
Figure 9: Correct and wrong connection for the power on/off control
5.1 Reset
WT32i may be reset from several sources: reset pin, power on reset, a UART break character or through
software configured watchdog timer.
At reset, the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state.
The chip status after a reset is as follows:
 Warm Reset: data rate and RAM data remain available
 Cold Reset: data rate and RAM data are not available
Table 13 shows the pin states of WT32i on reset. Pull-up (PU) and pull-down (PD) default to weak values
unless specified otherwise.