Specifications

Bluegiga Technologies Oy
Page 24 of 64
Pin Name / Group
I/O Type
No Core Voltage
Reset
Full Chip Reset
USB
Digital bi-directional
N/A
N/A
UART_RX
Digital input with PD
PD
PD
UART_CTS
UART_TX
Digital output with PU
PU
PU
UART_RTS
SPI_MOSI
Digital input with PD
PD
PD
SPI_CLK
SPI_MISO
Digital tristate output with
PD
SPI_CS
Digital input with PU
PU
PU
PCM_IN
Digital input with PD
PD
PD
PCM_CLK
Digital bi-directional with PD
PCM_SYNC
PCM_OUT
Digital tri-state output with
PD
GPIO
Digital bi-directional with
PU/PD
PD
PD
Table 13: Pin states on reset
5.1.1 Internal POR
WT32i has two internal POR circuits. One is internally to the BC5 chip. In BC5 the power on reset occurs
when the core supply voltage (output of the internal 1.5V regulator) falls below typically 1.26V and is released
when VDD_CORE rises above typically 1.31V.
Another POR circuit is embedded to the module and it keeps the module in reset until supply voltages have
stabilized. This is to prevent corruption of the internal flash memory during boot. The embedded POR is
shown in the figure Figure 1Figure 10.
Because the POR is based on a simple RC time constant it will not work if the supply voltage ramps very
slowly or if the reset pin is not connected to high impedance. It is recommended that the power ramp will not
take more than 10 msec. If the reset pin is connected to a host it is good to place a diode between the host
and the module as shown in Figure 11. A diode will prevent the host from pulling the reset low before the
internal flash has its supply stabilized.