Specifications

Bluegiga Technologies Oy
Page 42 of 64
WT32i
WS
SCK
I2S_IN
I2S_OUT
MCLK Generator
ASI
I2S CODEC
Figure 23: I
2
S scheme for WT32i
Bit
Mask
Name
Description
D[0]
0x0001
CONFIG_JUSTIFY_FORMAT
0 for left justified, 1 for right justified.
D[1]
0x0002
CONFIG_LEFT_JUSTIFY_DELAY
For left justified formats: 0 is MSB of SD
data occurs in the first SCLK period
following WS transition. 1 is MSB of SD
data occurs in the second SCLK period.
D[2]
0x0004
CONFIG_CHANNEL_POLARITY
For 0, SD data is left channel when WS
is high. For 1 SD data is right channel.
D[3]
0x0008
CONFIG_AUDIO_ATTEN_EN
For 0, 17-bit SD data is rounded down
to 16bits. For 1, the audio attenuation
defined in CONFIG_AUDIO_ATTEN is
applied over 24bits with saturated
rounding. Requires
CONFIG_16_BIT_CROP_EN to be 0.
D[7:4]
0x00F0
CONFIG_AUDIO_ATTEN
Attenuation in 6dB steps.
D[9:8]
0x0300
CONFIG_JUSTIFY_RESOLUTION
Resolution of data on SD_IN, 00=16bit,
01=20bit, 10=24bit, 11=Reserved. This
is required for right justified format and
with left justified LSB first.
D[10]
0x0400
CONFIG_16_BIT_CROP_EN
For 0, 17-bit SD_IN data is rounded
down to 16bits. For 1 only the most
significant 16bits of data are received.
Table 22: PSKEY_DIGITAL_AUDIO_CONFIG