User guide

VC709 Virtex-7 FPGA XT Connectivity TRD www.xilinx.com 67
UG962 (v3.0) December 20, 2014
Theoretical Estimate
Chapter 4
Performance Estimation
This chapter presents a theoretical estimation of performance. The best effort has been
made to achieve performance as close to this but it might not always be realistic.
Theoretical Estimate
PCIe–DMA
This section provides an estimate on performance of the PCIe link using Northwest Logic
Packet DMA.
PCIe is a serialized, high bandwidth, and scalable point-to-point protocol that provides
highly reliable data transfer operations. The maximum transfer rate for a PCIe
3.0-compliant device is 8 Gb/s per lane/direction. The actual throughput is lower due to
protocol overheads and system design trade-offs. For more information, see Understanding
Performance of PCI Express Systems (WP350) [Ref 10].
The PCIe link performance together with scatter-gather DMA is estimated under the
following assumptions:
• Each buffer descriptor points to a 4 KB data buffer space
• Maximum payload size (MPS) = 128 bytes
• Maximum read request size (MRRS) = 128 bytes
• Read completion boundary (RCB) = 64 bytes
• TLPs of 3DW considered without extended CRC (ECRC)—total overhead of 20 bytes
• One ACK assumed per TLP—DLLP overhead of 8 bytes
• Update FC DLLPs are not accounted for but they do affect the final throughput
slightly
The performance is projected by estimating the overheads and then calculating the
effective throughput by deducting the overheads.
The following conventions are used in the calculations below:
• MRD: Memory read transaction
• WR: Memory write transaction
• CPLD: Completion with data
• C2S: Card-to-System
•S2C: System-to-Card
Calculations are done considering unidirectional data traffic; that is either transmit (data
transfer from S2C) or receive (data transfer from C2S).