User guide

86 www.xilinx.com VC709 Virtex-7 FPGA XT Connectivity TRD
UG962 (v3.0) December 20, 2014
Appendix A: Register Descriptions
Tabl e A - 4 6: XGEMAC2 Address Filtering Control Register (0x9418)
Bit Mode
Default
Value
Description
0RW0 Promiscuous Mode Enable for XGEMAC2
31 RO 0 Receive FIFO Overflow status for XGEMAC2
Tabl e A - 4 7: XGEMAC2 MAC Address Lower Register (0x941C)
Bit Mode
Default
Value
Description
31:0 RW 32'hAABBCCDD MAC address lower
Tabl e A - 4 8: XGEMAC2 MAC Address Upper Register (0x9420)
Bit Mode
Default
Value
Description
15:0 RW 16'hEEFF MAC address upper
Tabl e A - 4 9: XGEMAC3 Address Filtering Control Register (0x9424)
Bit Mode
Default
Value
Description
0RW0 Promiscuous mode enable for XGEMAC3
31 RO 0 Receive FIFO overflow status for XGEMAC3
Tabl e A - 5 0: XGEMAC3 MAC Address Lower Register (0x9428)
Bit Mode
Default
Value
Description
31:0 RW 32'hAABBCCDD MAC address lower
Tabl e A - 5 1: XGEMAC3 MAC Address Upper Register (0x942C)
Bit Mode
Default
Value
Description
15:0 RW 16'hEEFF MAC address upper