SERVICE GUIDE ORDER NO. RRV1896 DVD PLAYER DV-505 DV-S9 DVD LD PLAYER DVL-909 CONTENTS 1. CIRCUIT DESCRIPTION ...................................... 2 2. CIRCUIT DESCRIPTIONS FOR DV-S9 AND DV-09 ............................... 10 3. TEST MODE ....................................................... 13 4. IC INFORMATION .............................................. 22 5. FL INFORMATION ..............................................
TA FA Slider TE GEN HA OEIC A/D Servo DSP EFM Decoder DMA CPU I/F Mechanism sense SW Mechanism Control CPU IC501 PD4889A CD Digital Out CD PCM Sub-code Buffer CD-ROM Sync gen. ECC & ID Reg. DRAM I/F (bus arbitor) IC101 PD4890A Key-SW & Display Display CPU CD D.
TA FA Slider Mechanism sense SW Loading Motor Spindle Motor Key-SW & Display DIRB DV-S9 Only A/D (COAXIAL) Digital In (OPTICAL) TE GEN HA OEIC IC301 TLC5540INS Display CPU IC101 PD4890A Servo DSP DMA CPU I/F DIGITAL INTERFACE RECEIVER SREO XSACK DRAM 8 DNR IC811 8 IC901 PD0259A DATA SELECTOR 8 10 AC IN HIBIT LEGATO S FILTER FILTER FILTER FILTER AUDIO POWER SUPPLY 96/24 DAC AMP. AMP. AMP. AMP.
DV-505, DVL-909, DV-S9 DVL-909 4Mbit DRAM VBR Buffer IC701 PD4833A LSI-11 SPDL Motor TA FA TA FA Slider Slider For CLD HA OEIC System CPU (32bit RISC) DRAM I/F (Bus Arbiter) Sync Demod A/D IC601 PD3381A IC702 HM514800CJ-7 IC603 IC602 IC604 FLASH ROM GUI ROM RAM CPU I/F ECC & ID Reg.
DV-505, DVL-909, DV-S9 IC802 MB811171622A -100FN DVD Y (IC815 1 ) 16Mbit SDRAM CODE Buffer (Video, Audio, Sub-picture,GUI) (from MECHA. CONT.
DV-505, DVL-909, DV-S9 1.2 EXPLANATION OF EACH MOVEMENT 1.2.1 Sequence Up to Playback DVD SETUP MIRR Modulation Measurement RF AGC ON T Servo ON SLDR Servo ON LD ON Sweep UP → Down F Gain Adj. T Gain Adj. Focus Lock AFB Adj. (Auto Focus Bias) Yes SPDL ACCEL Layer Det. ATB ON Lead-in Search PLAY 1.2.2 Focus Servo FE generated in the RF IC is sent to the Digital servo IC. For a DVD, the servo is turned on during the transition from “Up” to “Down” of the first-order sine wave.
DV-505, DVL-909, DV-S9 1.2.3 Tracking / Slider Servo ATB: The tracking balance compensation is • TRACKING / SLIDER SERVO achieved by outputting the offset from the TBAL output at pin 46 of the digital PICKUP servo IC, and by biasing the charge pump TE RF 4 resistor for phase-difference error of B1 5 IC101 RFIC. B2 6 RFIC OEIC The difference is detected by processing B3 7 TE at pin 34 of IC 201 with an internal B4 8 digital equalizer.
DV-505, DVL-909, DV-S9 1.2.5 Disc Determination Determination is achieved by checking the sine wave by sweeping the lens with the OE IC gain at L and the FSC error amplifier (SGC) at the default setting. If no sine wave is detected, checking is retried after switching the OE IC gain to H and increasing the gain of the FSC error amplifier (SGC). If no sine wave is detected again, it is regarded as the NO DISC condition. If one half of the sine wave detected at the first lens sweep is of a value less than 0.
DV-505, DVL-909, DV-S9 1.2.6 System Control (DVL-909) DVD MAIN 16 SI1,SO1 SCK1,XRDY 13 IC101 PD4890A Mode Control 22 (FL Cont.) 102,107,108,111 FLPB, KEYB IC601 PD3381A IC604 Work RAM System Cont. IC603 FLASH ROM IC602 GUI 4M ROM 21 IC801 MB86371 AV-Dec. MAD0–MAD7 Mech. Cont. (DVD) 77 POWER SUPPLY ASSY 8 72 26 IC501 PD4889A 65 LSI-11 19 IC701 PD4833A 142 151 Remote Sensor XRESET KEY POWER ON DATA,ADDRESS MAIN BUS 39 19 Loading Position SW SW1–3 9 21 56 Mech. Cont.
DV-505, DVL-909, DV-S9 2. CIRCUIT DESCRIPTIONS FOR DV-S9 AND DV-09 2.1 VIDEO SIGNAL PROCESSING BLOCK 2.1.1 PD0259A Block (3) Y/C-timing Adjustment The major purposes of the PD0259A block are; (1) Frame-correlative cyclic digital noise reduction (2) Horizontal and vertical contour compensation (3) Y/C timing adjustment (4) Frame freezing This function changes the output phase of the Y signal with respect to the Cb and Cr signals in units of the 13.5-MHz clock cycle (approx. 74 ns).
DV-505, DVL-909, DV-S9 2.1.3 Analog Video Signal Processing Block The video signals output from the built-in 10-bit DA converter of the M65677FP pass through a low-pass filter and amplifier, and are output from the DVD MAIN Assy and sent to the VOUT Assy. In the VOUT Assy, analog noise-reduction processing having three levels (OFF, low, and high) is initially applied only to the Y signal. This analog noise reduction is the same as that performed by conventional laser-disc players.
DV-505, DVL-909, DV-S9 2.2 DIRB BLOCK (DIRB ASSY) (DV-S9 ONLY) 2.3 96K, 24-Bit, HIBIT LEGATO S SYSTEM (AUDIO ASSY) The two major purposes of the DIRB block are the following: (1) Switching between data reproduced from a disc and a data signal in DAC mode (2) Data decoding in external input mode (DAC mode) All 16-bit and 20-bit sources are converted to 24-bit data by IC101, which lets a 24-bit data pass through.
DV-505, DVL-909, DV-S9 3. TEST MODE 3.1 HOW TO ENTER THE TEST MODE (5) Pause There is the three following methods in an enters of the test mode. 1. Short-circuit the terminals (TP6006 and TP6007) for test mode entry at the side of the system control IC (IC601) of DVDM ASSY, and turn the power on. 2. Input [ESC] key and [TEST/RANDOM] key of the test mode remote control unit in order under the power on condition. 3.
DV-505, DVL-909, DV-S9 (11) Tracking Close (20) Tilt Up 1. Press [STEP RVS] (50) key of the remote control unit in the play condition. 2. Switch the open/close by pressing [PLAY] key of the remote control unit or the player during the play (CD only). A manual moves in the going up direction when [SKIP FWD] (52) key of the remote control unit is pressed during the play at the time of tilt off. (21) Focus Jump + (12) Slider In 1.
DV-505, DVL-909, DV-S9 3.4 EXPANSION FUNCTION 1 3.5 EXPANSION FUNCTION 2 Set the reception mode of expansion function by pressing [TEST] (5E) key of the test mode remote control unit, then expansion function is able to execute by pressing the key of [0] to [9]. Indication for the most significant digit becomes "T" during the reception mode of expansion function. (This mode can on and off with toggle.
DV-505, DVL-909, DV-S9 Contents of Command Search address input (A to F) Search address clear Escape the search input mode During address input Key Name of Remote Control Unit PGM+1 to 6 During address input CLEAR A8-45 +10 A8-1F Condition Mode of Remote Control Unit Address = 0 Change the search address input mode (Off→absolute address→addition→subtraction→Off) ∗Use for other numerical value input.
DV-505, DVL-909, DV-S9 Special Mention Item (1) Indications for the spindle status are as follows: A/B : Spindle accelerator and brake FG : FG servo SRV : Rough, velocity/phase servo O_S : Offset addition, rough, velocity/phase servo (2) The movement of loading in/out starts from the tray open status. After that, this function is executed unless a play and close operation are done.
DV-505, DVL-909, DV-S9 • Description of Each Item on the Display (1) Address indication The address being traced is displayed in number. DVD : ID indication (hexadecimal number, 8 digits) [∗∗∗∗∗∗∗∗] ∗∗∗∗] CD/LD (CLV) : A-TIME (min. sec.) [ ∗∗∗∗∗] LD (CAV) : FRAME [ (Note : For DVDs, decimal-number indication is possible.
DV-505, DVL-909, DV-S9 (20) Revision of the DVD mechanism controller [M:∗.∗∗∗/∗.∗∗∗] Revision number of the external ROM part (flash ROM) of the DVD mechanism controller Revision of the internal ROM (core part) of the DVD mechanism controller (21) Revision of the CLD mechanism controller [L:∗.∗∗∗] Using the Function in Test Mode (The Remote Control Keys to be Used are Indicated in Brackets) (1) Set the CD to trace (playback) state.
DV-505, DVL-909, DV-S9 Using the Function in Test Mode 3.8.3 Startup Sequence The basic flow is shown below. The parentheses indicate a limitation: “base” represents base models, such as the DV-505 and DV-S9, and “compatibles” represents DVD-LD compatible models, such as the DVL-909. (1) Closes the tray. (2) Runs the tilt servo for 1.5 seconds (compatibles). (3) Detects the peak. (4) Distinguishes the disc. (5) SGC (6) Turns on the focus servo. (7) Turns on the tilt servo (compatibles).
DV-505, DVL-909, DV-S9 3.8.9 PLAY AGC Overview The SGC voltage is adjusted during playback according to the RF signal level. (For details on SGC, see section 3.8.6.) Only for CDs in basic models, such as the DV-505 (including the DV-S9), this adjustment is made only once immediately after AFB during startup. In Test mode, it synchronizes with AGC ON/OFF. The operation is achieved through adjustment in the Servo DSP (LC78650), and the SGC voltage is output via AUX0 (pin 44).
DV-505, DVL-909, DV-S9 4. IC INFORMATION • The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
DV-505, DVL-909, DV-S9 • Pin Function No.
DV-505, DVL-909, DV-S9 No.
DV-505, DVL-909, DV-S9 PD0260A2, PD0261A2 (CLDM ASSY : IC101)(DVL-909 ONLY) • Mechanism Control IC • Pin Function No.
DV-505, DVL-909, DV-S9 No.
DV-505, DVL-909, DV-S9 LA9700M (DVDM ASSY : IC101) • RF IC RFOUT PHC BHC PHI BHI PH BH GND TC DEPC DLPC DEF DEFI RFO EQI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Scratch Detection REF 48 BPI1 VCC PH 50k BH PH – + 50k REFI 2 REF BH VCC 47 VCC + – 26p 80k 80k RFI 3 REF 46 BPO1 45k 80k 80k LIM PD1 5 LIM PD PD2 6 LIM PD PD3 7 LIM 45 EQB 1k PDRF 4 – + 3k PDRF– 1 50k REF • Block Diagram REF 3k + – 44 BPO2 40k 40k – + PD 40k 40k PD4
DV-505, DVL-909, DV-S9 BA6195FP (DVDM ASSY : IC161) • Spindle Driver 18 17 16 15 14 NC GND Driver mute NC 19 NC 20 NC 21 NC VCC 22 NC NC MUTE 23 GND NC 24 GND OPIN+ 25 NC OPIN– • Block Diagram TSD GND NC NC NC VCC IN Level shift 10K 10K 10K 10K 7 8 9 10 11 12 13 DROUT+ BIAS NC DROUT– NC 6 NC NC NC 5 NC NC 4 NC NC 3 NC NC 2 10K NC 1 DRIN NC DRIN' NC OPOUT 10K • Pin Function No. Pin Name 1 OPOUT 2 N.C. 3 N.C.
DV-505, DVL-909, DV-S9 LC78650E-P (DVDM ASSY : IC201)(DVL-909 only) • Servo DSP LSI • Block Diagram FE 35 49 FDO 50 TDO TE 34 TILTE 31 MPX RF_PH 32 8bit A/D Servo Processor (16×16+32→32) 47 SLDO 8bit D/A 48 SPDO 46 TBAL RF_BH 33 45 TILTDO 44 AUXO JITT 30 HFL 63 61 VREF CMP 26 DRF TES 28 Track Counter 55 DVD_CDB 1 PP5/SYNC PP7/EVNT 58 Event Counter LCD Driver PP6/FG 57 SLCIST1,2 36,37 EFMIN 41 SLCO1,2 38,39 EFMOUT 3 PCKIST1,2 89,90 CDFR 93 DVDFR 92 PD01-3 85-87 JV 94 LEFM 2 PCK 95 VR
DV-505, DVL-909, DV-S9 • Pin Function No. 1 Pin Name PP5/SYNC I/O Function I/O General-purpose port input/output / DVD sync. signal input 2 LEFM O Output the state that cut and out a signal which was binary-stated value EFM/EFM + with PCK. 3 EFMOUT O Output the state that was binary-stated value EFM/EFM + .
DV-505, DVL-909, DV-S9 No.
DV-505, DVL-909, DV-S9 PD4889A (DVDM ASSY : IC501) • Mechanism Control IC • Pin Function No. Pin Name No. Pin Name I/O 1 LODDRV I/O Loading motor drive output I/O Function 33 XDSPRST − Reset pulse for servo DSP "L" 2 DVD/XCD O 34 ASTB O Address strobe of multiplexed address/data bus "H" 3 AGOFF O Turn AGC of RF IC to OFF for "H" 35 XRST I CPU reset input "L" 36 SBSY Subcode frame sync.
DV-505, DVL-909, DV-S9 SRM2B256SLMX70 (DVDM ASSY : IC502) • 256 K SRAM (For Mechanism Control IC) • Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 10 CS 20 Control Logic OE 22 OE, WE WE 27 Control Logic 9 8 7 9 5 4 3 25 24 Address Buffer 6 Line Decoder 512 Memory-Cell Array 512×64×8 64×8 21 23 2 6 26 Row Decoder 64 Row Gate 1 CS 8 14 18 11 12 13 15 16 17 18 19 Vss VDD I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O Buffer • Pin Function No.
DV-505, DVL-909, DV-S9 VYW1536 (DVDM ASSY : IC603)(DV-505 and DVL-909 only) • Flash ROM • Block Diagram DQ0-DQ15 RY/BY 15-22, 24-31 1 RY/BY BUFFER RY/BY ERASE CIRCUIT WE BYTE RESET INPUT/OUTPUT BUFFER 43 33 CONTROL CIRCUIT 44 WRITE CIRCUIT CHIP ENABLE STB OUTPUT ENABLE CIRCUIT 12 14 LOW VCC DET. CIRCUIT STB WRITE/ERASE PULSE TIMER 2-11, A0-A18 34-42 A-1 31 ADDRESS LATCH CE OE DATA LATCH Y DECODER X DECODER Y GATE 8,388,608 CELL MATRIX • Pin Function No.
DV-505, DVL-909, DV-S9 PD3381A (DVDM ASSY : IC601) A16 A17 A18 A19 A20 A21 CS0 CS1/CASH CS2 CS3/CASL PA0/CS4/TIOCA0 PA1/CS5/RA5/RAS PA2/CS6/TIOCB0 PA3/CS7/WAIT PA4/WRL(WR) PA5/WRH(LBS) PA6/RD PA7/BACK PA8/BREQ PA9/AH/IRQOUT/ADTRG PA10/DPL/TIOCA1 PA11/DPH/TIOCB1 PA12/IRQ0/DACK0/TCLKA PA14/IRQ2/DACK1 PA15/IRQ3/DREQ1 • Block Diagram PA13/IRQ1/DREQ0/TCLKB • System Control CPU 69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 51 50 49 48 47 46 45 44 42 41 PORT A ADDRESS RES 79 39
DV-505, DVL-909, DV-S9 • Pin Function No.
DV-505, DVL-909, DV-S9 No.
DV-505, DVL-909, DV-S9 No.
DV-505, DVL-909, DV-S9 MB86371 (DVDM ASSY : IC801) • MPEG2 Decoder LSI For DVD • Block Diagram Exclusive Parallel port Input Signal CPU CPU Interface System Decoder Block 16Mbit SDRAM Memory Controller Block Internal Bus Video Decoder Block Sync.
DV-505, DVL-909, DV-S9 • Pin Function No. Pin Name I/O Function No. Pin Name 1 CLKSEL I ON/OFF signal of PLL ("H" : ON, "L" : OFF) 27 VDD 2 DIGCPN7 O Digital component signal output (MSB) Digital Y signal output (9-bit) (MSB) 28 DIGCOMP4 3 VSS − GND 29 DIGCOMP3 4 DIGCPN6 30 DIGCOMP2 5 DIGCPN5 31 DIGCOMP1 6 DIGCPN4 7 DIGCPN3 8 9 O Digital component signal output Digital Y signal output (9-bit) I/O − O Function 3.
DV-505, DVL-909, DV-S9 No. Pin Name 53 DAIIN I/O Function No. Pin Name I Digital data input of external input (SPDIF) 92 HADRS10 54 CDDATA I Audio data input of external input (correspond to CD) 93 HADRS9 55 CDLR I Data channel clock input of external input (correspond to CD) 94 HADRS8 56 CDBCK I Data clock input of external input (correspond to CD) 95 HADRS7 57 AODATA3 58 AODATA2 I/O Function I CPU address bus signal (MSB) I CPU address bus signal 96 VSS − GND − 3.
DV-505, DVL-909, DV-S9 Pin Name I/O 131 VDD No. Pin Name I/O − 3.
DV-505, DVL-909, DV-S9 MB811171622A-100FN (DVDM ASSY : IC802) • Code Buffer (16M bit SDRAM) • Block Diagram A0-A11, AP DQ0-DQ15 Clock Buffer 34 To Blocks Bank 1 17 16 Command Decoder Control Signal Latch CAS WE 15 Address Buffer/ Register & Bank Select 1 Pin Name VCC 2 DQ0 3 DQ1 4 VSSQ 5 DQ2 6 DQ3 7 VCCQ 8 DQ4 DRAM Core (2,048×256×16) Mode Register Row Address Column Address Counter 14 36 Column Address I/O I/O Data Buffer/ Register 1,7,13,25,38,44 4,10,26,41,47,50 VC
DV-505, DVL-909, DV-S9 CY2081SL-611 (DVDM ASSY : IC813) • Clock Generate IC • Block Diagram XTALIN XTALOUT 3 GND VDD 2 OE/PD/FS/SUSPEND 8 4 Refference Oscillator PLL1 PLL2 7 PLL3 EPROMConfigurable Multiplexer and Drive Logic 1 CLKA 5 CLKB 6 CLKC • Pin Function No.
DV-505, DVL-909, DV-S9 PD2058A ( DVDM ASSY : IC901 )(DV-505 and DVL-909 only) • Digital Signal Processor For Audio 4,31 5,14,34,52 Offset RAM 64w×16b Coefficient ROM 256w×16b Coefficient RAM 320w×16b Data RAM 128w×24b VSS 13 12 VDD 1–3,6–11, 53–60 VSSR VDDR 42–44 TPS16 45 TPS0 TES0 TES2 RST • Block Diagram Delay RAM 4096w×16b Delay RAM Address Generating Circuit Interface bus Data bus Work register bus 24b Program Counter Logical Arithmetic Unit(LU) Program ROM 1024w×32b 16b 36 P
DV-505, DVL-909, DV-S9 No. Pin Name 12 VSSR I/O Function − Ground pin for internal delay RAM (DLRAM) 13 VDDR − Power supply pin for internal delay RAM (DLRAM) 14 VSS − Ground pin O Serial data output pin Output data length is able to select the 24-bit or 16-bit by controlling the microprocessor. I Serial data input pin Input data length is able to select the 24-bit or 16-bit by controlling the microprocessor.
DV-505, DVL-909, DV-S9 5.