Specifications

19
Reference
Characteristics
Min
Typ
Max
Unit
1
PCM bit clock frequency
-
-
12
MHz
2
PCM bit clock LOW
41
-
-
ns
3
PCM bit clock HIGH
41
-
-
ns
4
PCM_SYNC setup
8
-
-
ns
5
PCM_SYNC hold
8
-
-
ns
6
PCM_OUT delay
0
-
25
ns
7
PCM_IN setup
8
-
-
ns
8
PCM_IN hold
8
-
9
Delay from rising edge of PCM_BCLK during last bit period
to PCM_OUT becoming high impedance
0
-
25
ns
PCM Timing Diagram(Long Frame Sync, Slave mode)
3.3 I2S Interface
3.3.1 I2S Interface Timing
The I2S interface supports both master and slave modes. The I2S signals are:
■ I2S clock: I2S SCK
■ I2S Word Select: I2S WS
■ I2S Data Out: I2S SDO
■ I2S Data In: I2S SDI
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always
stays as an output. The channel
word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with
the MSB of the I2S bus, per the
I2S specification. The MSB of each data word is transmitted one bit clock cycle after the I2S WS
transition, synchronous with the falling
edge of bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is
transmitted when I2S WS is high.
Data bits sent by the BCM-DC100-AS are synchronized with the falling edge of I2S_SCK and should be
sampled by the receiver on
the rising edge of I2S_SSCK.
The clock rate in master mode is either of the following:
■ 48 kHz x 32 bits per frame = 1.536 MHz
■ 48 kHz x 50 bits per frame = 2.400 MHz