Specifications
20
The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any
clock rate is supported
to a maximum of 3.072 MHz. Timing values specified in Table 25 are relative to high and low threshold levels.
Transmitter
Receiver
Lower LImit
Upper Limit
Lower Limit
Upper Limit
Min
Max
Min
Max
Min
Max
Min
Max
Clock Period T
Ttr
Tr
Note 22
Master Mode: Clock generated by transmitter or receiver
HIGH tHC
0.35Ttr
0.35Ttr
Note 23
LOWtLC
0.35Ttr
0.35Ttr
Note 23
Slave Mode: Clock accepted by transmitter or receiver
HIGH tHC
0.35Ttr
0.35Ttr
Note 24
LOW tLC
0.35Ttr
0.35Ttr
Note 24
Rise time tRC
0.15Ttr
Note 25
Transmitter
Delay tdtr
0.8T
Note 26
Hold time thtr
0
Note 26
Receiver
Setup time tsr
0.2Tr
Note 27
Hold time thr
0
Note 27
Note: The time periods specified in Figure 21 and Figure 22 are defined by the transmitter speed. The receiver
specifications must match transmitter performance.
Notes
22. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data
transfer rate.
23. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and
tLC are specified with
respect to T.
24. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So
long as the minimum
periods are greater than 0.35Tr, any clock that meets the requirements can be used.
25. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can
result in tdtr not exceeding
tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as
the clock rise-time
tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr.
26. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving
the receiver sufficient
setup time.
27. The data setup and hold time must not be less than the specified receiver setup and hold time.