TTCAN User’s Manual Revision 1.6 TTCAN IP Module User’s Manual Revision 1.6 manual_about.fm 11.11.02 Robert Bosch GmbH Automotive Electronics Semiconductors and Integrated Circuits Digital CMOS Design Group BOSCH 11.11.
TTCAN User’s Manual Revision 1.6 Copyright Notice and Proprietary Information Copyright © 1998, 1999, 2002 Robert Bosch GmbH. All rights reserved. This software and manual are owned by Robert Bosch GmbH, and may be used only as authorized in the license agreement controlling such use.
TTCAN User’s Manual Revision 1.6 TTCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1. Change Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1. Current Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2. Change History . . . . .
TTCAN User’s Manual Revision 1.6 3.4. Message Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.1. Interrupt Register (addresses 0x09 & 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.2. Transmission Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.3. New Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.4.
TTCAN User’s Manual Revision 1.6 4.2.2. Configuration of the Message Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2.2.1. Configuration of a Transmit Object for Data Frames . . . . . . . . . . . . . . . . . . 54 4.2.2.2. Configuration of a Single Receive Object for Data Frames . . . . . . . . . . . . . 54 4.2.2.3. Configuration of a FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.2.4.
User’s Manual TTCAN Revision 1.6 1. About this Document 1.1 Change Control 1.1.1 Current Status Revision 1.6 1.1.2 Change History Issue Date By Change Draft 0.0 Revision 0.1 Revision 0.2 Revision 1.0 Revision 1.1 Revision 1.2 Revision 1.3 Revision 1.4 Revision 1.5 Revision 1.6 30.06.00 12.01.01 21.10.00 29.11.00 11.12.00 13.12.00 17.01.01 30.04.01 12.10.01 11.11.02 F. Hartwich F. Hartwich F. Hartwich F. Hartwich F. Hartwich F. Hartwich F. Hartwich F. Hartwich F. Hartwich F.
User’s Manual TTCAN Revision 1.6 1.5 Terms and Abbreviations This document uses the following terms and abbreviations. Meaning CAN Controller Area Network BSP Bit Stream Processor BTL Bit Timing Logic CRC Cyclic Redundancy Check Register DLC Data Length Code EML Error Management Logic FSE Frame Synchronisation Entity FSM Finite State Machine NTU Network Time Unit TTCAN Time Triggered CAN manual_about.fm Term BOSCH - 7/77 - 11.11.
TTCAN User’s Manual Revision 1.6 2. Functional Description 2.1 Functional Overview The TTCAN is a CAN IP module that can be integrated as stand-alone device or as part of an ASIC. It is described in VHDL on RTL level, prepared for synthesis. It consists of the components (see figure 1) CAN_Core, Message RAM, Message Handler, Control Registers, Module Interface, and, for the time triggered function, Trigger Memory and Frame Synchronisation Entity.
User’s Manual TTCAN Revision 1.6 2.2 Block Diagram CAN_TX CAN_Core CAN_RX CAN-Message Clock DataIN DataOUT Message RAM (single ported) CPU IFC Register 2 Address Module Interface Control CPU IFC Register 1 Reset Message Handler Wait Trigger Memory Interrupt Trigger SWT, EVT TTCAN - Frame Synchronisation Entity TMI TTCAN Figure 1: Block Diagram of the TTCAN CAN_Core CAN Protocol Controller and Rx/Tx Shift Register, handles all ISO 11898-1 protocol functions. manual_about.
TTCAN User’s Manual Revision 1.6 2.3 Operating Modes 2.3.1 Software Initialisation The software initialization is started by setting the bit Init in the CAN Control Register, either by software or by a hardware reset, or by going Bus_Off. While Init is set, all message transfer from and to the CAN bus is stopped, the status of the CAN bus output CAN_TX is recessive (HIGH). The counters of the EML are unchanged. Setting Init does not change any configuration register.
User’s Manual TTCAN Revision 1.6 set to not valid any time, even when their requested transmission is still pending. The old data will be discarded when a message is updated before its pending transmission has started. Depending on the configuration of the Message Object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier. 2.3.3 Disabled Automatic Retransmission According to the CAN Specification (see ISO11898, 6.3.
User’s Manual TTCAN Revision 1.6 LBack Loop Back Mode one Loop Back Mode is enabled. zero Loop Back Mode is disabled. Silent Silent Mode one The module is in Silent Mode zero Normal operation. NoRAM No Message RAM Mode one IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. zero No Message RAM Mode disabled, normal Message RAM usage. WdOff Disable Watchdog one The Watchdog disabled. zero The Watchdog is enabled, after Initialization has finished (Init = 0).
User’s Manual TTCAN Revision 1.6 2.3.4.4 Loop Back Mode The CAN_Core can be set in Loop Back Mode by programming the Test Register bit LBack to one. In Loop Back Mode, the CAN_Core treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into a Receive Buffer. Figure 3 shows the connection of signals CAN_TX and CAN_RX to the CAN_Core in Loop Back Mode.
TTCAN User’s Manual Revision 1.6 2.3.4.6 Software control of Pin CAN_TX Four output functions are available for the CAN transmit pin CAN_TX. Additionally to its default function – the serial data output – it can drive the CAN Sample Point signal to monitor the CAN_Core’s bit timing and it can drive constant dominant or recessive values. The last two functions, combined with the readable CAN receive pin CAN_RX, can be used to check the CAN bus’ physical layer.
User’s Manual TTCAN Revision 1.6 3. Programmer’s Model The TTCAN module allocates an address space of 256 bytes. The registers are organized as 16-bit registers, with the high byte at the odd address and the low byte at the even address. The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts between CPU accesses and message reception/transmission. manual_about.
User’s Manual TTCAN manual_about.fm Address Name Reset Value Revision 1.6 Note CAN Base+0x48 IF2 Arbitration 1 0x0000 CAN appl.
User’s Manual TTCAN Revision 1.6 3.2 CAN Protocol Related Registers These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and the configuration of the CAN bit timing and provide status information. 3.2.1 CAN Control Register (addresses 0x01 & 0x00) 15 res r 14 res r 13 res r 12 res r 11 res r 10 res r 9 res r 8 res r 7 Test rw 6 5 CCE DAR rw rw 4 res r 3 EIE rw 2 SIE rw 1 IE rw 0 Init rw Test Test Mode Enable one Test Mode.
User’s Manual TTCAN Revision 1.6 3.2.2 Status Register (addresses 0x03 & 0x02) 15 res r BOff 14 res r 13 res r 12 res r 11 res r 10 res r 9 res r 8 res r 7 6 5 4 3 BOff EWarn EPass RxOk TxOk r r r rw rw 2 1 LEC rw 0 Bus_Off Status one The CAN module is in Bus_Off state. zero The CAN module is not Bus_Off. EWarn Warning Status one At least one of the error counters in the EML has reached the error warning limit of 96. zero Both error counters are below the error warning limit of 96.
User’s Manual TTCAN Revision 1.6 The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error. The unused code ‘7’ may be written by the CPU to check for updates. 3.2.2.
User’s Manual TTCAN Revision 1.6 BRP Baud Rate Prescaler 0x00-0x3F The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [0 … 63]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. This register is only writable if bits CCE and Init in the CAN Control Register are set.
User’s Manual TTCAN Revision 1.6 single transfer. This transfer, performed in parallel on all selected parts of the Message Object, guarantees the data consistency of the CAN message. Figure 6 shows the structure of the two Interface Register sets. The function of the two Interface Register sets is identical (except for test mode NoRAM). The second interface register set is provided to serve application programming.
User’s Manual TTCAN Revision 1.6 ClrIntPnd Clear Interrupt Pending Bit Note : When writing to a Message Object, this bit is ignored. TxRqst/NewDatAccess Transmission Request Bit one set TxRqst bit zero TxRqst bit unchanged Note : If a transmission is requested by setting TxRqst/NewDat in the IFx Command Mask Register, bit TxRqst in the IFx Message Control Register will be ignored. Data A Access Data Bytes 0-3 one transfer Data Bytes 0-3 to Message Object. zero Data Bytes 0-3 unchanged.
User’s Manual TTCAN Revision 1.6 6 CAN_CLK periods, the transfer between the Interface Register and the Message RAM has completed and the Busy bit is cleared to ‘0’. The upper limit of the wait time occurs when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage. If the CPU-IFC is implemented with the wait-function, the CPU is halted while the Busy bit is set.
User’s Manual TTCAN Revision 1.6 3.3.3.3 IFx Message Control Registers IF1 Message Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (addresses 0x1D & 0x1C) NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB MSC2-0 DLC3-0 IF2 Message Control Register NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB MSC2-0 DLC3-0 (addresses 0x4D & 0x4C) rw rw rw rw rw rw rw rw rw rw rw 3.3.3.
TTCAN User’s Manual Revision 1.6 ID28-0 Message Identifier ID28 - ID0 29-bit Identifier (“Extended Frame”). ID28 - ID18 11-bit Identifier (“Standard Frame”). Msk28-0 Identifier Mask one The corresponding identifier bit is used for acceptance filtering. zero The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. Xtd Extended Identifier one The 29-bit (“extended”) Identifier will be used for this Message Object.
TTCAN User’s Manual Revision 1.6 NewDat New Data one The Message Handler or the CPU has written new data into the data portion of this Message Object. zero No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. MsgLst Message Lost (only valid for Message Objects with direction = receive) one The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
User’s Manual TTCAN Data 0 1st data byte of a CAN Data Frame Data 1 2nd data byte of a CAN Data Frame Data 2 3rd data byte of a CAN Data Frame Data 3 4th data byte of a CAN Data Frame Data 4 5th data byte of a CAN Data Frame Data 5 6th data byte of a CAN Data Frame Data 6 7th data byte of a CAN Data Frame Data 7 8th data byte of a CAN Data Frame Revision 1.
User’s Manual TTCAN Revision 1.6 3.4.2 Transmission Request Registers Transmission Request 1 Register (addresses 0x81 & 0x80) Transmission Request 2 Register (addresses 0x83 & 0x82) 15 14 13 12 11 10 TxRqst16-9 TxRqst32-25 r 9 8 7 6 5 4 3 2 TxRqst8-1 TxRqst24-17 r 1 0 TxRqst32-1Transmission Request Bits (of all Message Objects) one The transmission of this Message Object is requested and is not yet done. zero This Message Object is not waiting for transmission.
User’s Manual TTCAN Revision 1.6 3.4.5 Message Valid 1 Register Message Valid 1 Register (addresses 0xB1 & 0xB0) 15 14 13 12 11 10 MsgVal16-9 MsgVal32-25 r Message Valid 2 Register (addresses 0xB3 & 0xB2) 9 8 7 6 5 4 3 2 MsgVal8-1 MsgVal24-17 r 1 0 MsgVal32-1Message Valid Bits (of all Message Objects) one This Message Object is configured and should be considered by the Message Handler. zero This Message Object is ignored by the Message Handler.
User’s Manual TTCAN Revision 1.6 In the Trigger Memory, the Triggers must be sorted according to their Time_Marks. There may not be two Triggers that are active at the same Cycle Time and Cycle_Count. For details see chapter 5.1.3.
User’s Manual TTCAN Revision 1.6 EECS Enable External Clock Synchronisation one TUR Configuration (NumCfg only) may be updated during TTCAN operation. zero TUR Configuration may not be updated. TTMode TTCAN Operation Mode 0x0 TTMode_0 Event driven CAN Communication (default mode). 0x1 TTMode_1 Configuration Mode. 0x2 TTMode_2 Strictly Time Triggered Operation. 0x3 TTMode_3 Event Synchronised Time Triggered Operation.
User’s Manual TTCAN CCM Revision 1.6 Cycle_Count_Max (Number of last Basic Cycle in the Matrix Cycle) 0x00 1 Basic Cycle in the Matrix Cycle. 0x01 2 Basic Cycles in the Matrix Cycle. 0x03 4 Basic Cycles in the Matrix Cycle. 0x07 8 Basic Cycles in the Matrix Cycle. 0x0F 16 Basic Cycles in the Matrix Cycle. 0x1F 32 Basic Cycles in the Matrix Cycle. 0x3F 64 Basic Cycles in the Matrix Cycle. other values reserved. 3.5.
User’s Manual TTCAN Revision 1.6 Any number of bits may be written to ‘0’ (cleared) at the same time. Bits that are written to ‘1’ remain unchanged. 15 CfE rw 14 13 ApW WTr rw rw 12 IWT rw 11 CEL rw 10 TxO rw 9 8 TxU GTE rw rw 7 6 5 4 Dis GTW SWE TMI rw rw rw rw 3 SoG rw 2 1 0 CSM SSM SBC rw rw rw CfE Config Error Set when an error is found in the Trigger List. ApW Application Watchdog Set when the application watchdog was not served in time.
User’s Manual TTCAN Revision 1.6 3.5.9 TT Global Time Register (addresses 0x35 & 0x34) 15 14 13 12 11 10 9 8 7 Global_Time 6 5 4 r 3 2 1 0 3 2 1 0 3 2 1 0 r Global_Time Global Time of the TTCAN network 0x0000-0xFFFF Actual Global Time value. 3.5.10 TT Cycle Time Register (addresses 0x37 & 0x36) 15 14 13 12 11 10 9 8 7 Cycle_Time 6 5 4 r r Cycle_Time Cycle Time of the TTCAN basic cycle 0x0000-0xFFFF Actual Cycle Time value. 3.5.
User’s Manual TTCAN Revision 1.6 3.5.13 TT Cycle Count Register (addresses 0x3D & 0x3C) 15 14 13 12 11 reserved r 10 9 8 7 6 5 4 3 2 C_Cnt5-0 r res r 1 0 C_Cnt5-0 Cycle_Count 0x00-0x3F The number of the actual Basic Cycle in the System Matrix. 3.5.
User’s Manual TTCAN Revision 1.6 3.5.16 TUR Denominator Configuration Register (addresses 0x59 & 0x58) 15 14 13 12 11 10 9 res r 8 7 6 5 DenomCfg[13…0] rw 4 3 2 1 0 DenomCfg[13…0] TUR Denominator Configuration 0x0000 Illegal value. 0x0001-0x3FFF DenomCfg[13… 0]. The length of the NTU is given by (NumCfg • System Clock Period) = (DenomCfg • NTU), or NTU = System Clock Period • NumCfg/DenomCfg. DenomCfg is set to 0x1000 by hardware reset and it may not be written to 0x0000.
User’s Manual TTCAN Revision 1.6 3.5.19 TT Global Time Preset Register (addresses 0x65 & 0x64) 15 14 13 12 11 10 9 8 7 GTDiff 6 5 4 rw 3 2 1 0 rw GTDiff Global Time Preset 0x0000-0x7FFF Master_Ref_Mark = Master_Ref_Mark + GTDiff. 0x8000 reserved. 0x8001-0xFFFF Master_Ref_Mark = Master_Ref_Mark - (0x10000-GTDiff). The Global Time Preset takes effect when the node is the current Time Master and when ‘1’ is written to SGT in the TT Clock Control register.
User’s Manual TTCAN Revision 1.6 TMC Time Mark Compare 0x0 No Time Mark interrupt is generated. 0x1 Time Mark interrupt if (Time Mark = Cycle Time). 0x2 Time Mark interrupt if (Time Mark = Local Time). 0x3 Time Mark interrupt if (Time Mark = Global Time). DET Disable External Time Mark Port one The Time Mark port is disabled. zero The Time Mark port is enabled. ECS External Clock Synchronisation The External Clock Synchronisation takes effect when ‘1’ is written to ECS.
User’s Manual TTCAN Revision 1.6 3.5.22 TT Time Mark Register (addresses 0x6D & 0x6C) 15 14 13 12 11 10 9 8 7 TMark 6 5 4 rw TMark 3 2 1 0 rw Time Mark 0x0000-0xFFFF An interrupt is generated when the time base indicated by TMC (Cycle Time, Local Time, or Global Time) has the same value as Time Mark. Note : The Time Mark register can only be written while the time mark interrupt is disabled by TMC = 0. 3.5.
TTCAN User’s Manual Revision 1.6 basic cycle will continue until its last time window. The time after the last time window is the Gap time. In nodes that are time slaves, the Gap bit will remain at ‘0’. In the actual time master and in potential time masters, the Gap bit will be set when the last basic cycle has finished and the Gap time starts. The Gap is finished by setting FGp to ‘1’. There are three ways to set FGp. FGp can be set by the CPU directely.
TTCAN User’s Manual Revision 1.6 4. CAN Application The TTCAN module can emulate a C_CAN module in ordinary event driven ISO 11898-1 CAN communication. C_CAN software can also be used for the TTCAN, provided that the TTCAN’s application watchdog is disabled in the configuration phase, as described in chapter 2.3.4.2. The registers of the TTCAN module are subdivided into three classes: configuration registers, status registers, and application registers.
User’s Manual TTCAN Revision 1.6 When the CPU initiates a data transfer between the IFx Registers and Message RAM, the Message Handler sets the Busy bit in the respective Command Request Register to ‘1’. After the transfer has completed, the Busy bit is set back to ‘0’ (see figure 8). If the optional waitfunction is implemented in the module’s CPU interface, the CPU is halted while the Busy bit is set to ‘1’, see chapter 6.2.
TTCAN User’s Manual Revision 1.6 4.1.3 Acceptance Filtering of Received Messages When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely shifted into the shift register of the CAN_Core, the Message Handler FSM starts the scanning of the Message RAM for a matching valid Message Object. To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit is loaded with the arbitration bits from the CAN_Core shift register.
TTCAN User’s Manual Revision 1.6 Received messages with identifiers matching to a FIFO Buffer are stored into a Message Object of this FIFO Buffer, starting with the Message Object with the lowest message number. When a message is stored into a Message Object of a FIFO Buffer the NewDat bit of this Message Object is set. By setting NewDat while EoB is ‘0’ the Message Object is locked for further write accesses by the Message Handler until the CPU has cleared the NewDat bit.
User’s Manual TTCAN Revision 1.6 4.2.1 Configuration of the Bit Timing Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the performance of a CAN network can be reduced significantly. In many cases, the CAN bit synchronisation will amend a faulty configuration of the CAN bit timing to such a degree that only occasionally an error frame is generated.
User’s Manual TTCAN Revision 1.6 A given bit rate may be met by different bit time configurations, but for the proper function of the CAN network the physical delay times and the oscillator’s tolerance range have to be considered.
TTCAN User’s Manual Revision 1.6 transmits a recessive bit. The dominant bit transmitted by node B will arrive at node A after the delay(B_to_A). Due to oscillator tolerances, the actual position of node A’s Sample Point can be anywhere inside the nominal range of node A’s Phase Buffer Segments, so the bit transmitted by node B must arrive at node A before the start of Phase_Seg1. This condition defines the length of Prop_Seg.
User’s Manual TTCAN Revision 1.6 When the phase error of the edge which causes Resynchronisation is negative, Phase_Seg2 is shortened. If the magnitude of the phase error is less than SJW, Phase_Seg2 is shortened by the magnitude of the phase error, else it is shortened by SJW. When the magnitude of the phase error of the edge is less than or equal to the programmed value of SJW, the results of Hard Synchronisation and Resynchronisation are the same.
User’s Manual TTCAN Revision 1.6 In the first example an edge from recessive to dominant occurs at the end of Prop_Seg. The edge is “late” since it occurs after the Sync_Seg. Reacting to the “late” edge, Phase_Seg1 is lengthened so that the distance from the edge to the Sample Point is the same as it would have been from the Sync_Seg to the Sample Point if no edge had occurred.
User’s Manual TTCAN Revision 1.6 4.2.1.4 Oscillator Tolerance Range The oscillator tolerance range was increased when the CAN protocol was developed from version 1.1 to version 1.2 (version 1.0 was never implemented in silicon). The option to synchronise on edges from dominant to recessive became obsolete, only edges from recessive to dominant are considered for synchronisation. The only CAN controllers to implement protocol version 1.
TTCAN User’s Manual Revision 1.6 In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to be programmed to a numerical value that is one less than its functional value; so instead of values in the range of [1…n], values in the range of [0…n-1] are programmed. That way, e.g. SJW (functional range of [1…4]) is represented by only two bits.
User’s Manual TTCAN Revision 1.6 If more than one configuration is possible, that configuration allowing the highest oscillator tolerance range should be chosen. CAN nodes with different system clocks require different configurations to come to the same bit rate. The calculation of the propagation time in the CAN network, based on the nodes with the longest delay times, is done once for the whole network. The CAN system’s oscillator tolerance range is limited by that node with the lowest tolerance range.
User’s Manual TTCAN Revision 1.6 4.2.1.8 Example for Bit Timing at low Baudrate In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s. 1 µs = 2 • tCAN_CLK 200 80 220 1 ns ns ns µs = 1 • tq tSJW 4 µs = 4 • tq tTSeg1 5 µs = tProp + tSJW tTSeg2 4 µs = Information Processing Time + 3 • tq tSync-Seg 1 µs = 1 • tq bit time 10 µs = tSync-Seg + tTSeg1 + tTSeg2 1.
User’s Manual TTCAN Revision 1.6 The CPU may poll all MessageObject’s NewDat and TxRqst bits in parallel, in the New Data x Registers and in the Transmission Request x Registers. Polling is made easier if all Transmit Objects are grouped at the low numbers, all Receive Objects are grouped at the high numbers. The internal prioritisation of the Transmit Objects is controlled by their Message Number, so the most urgent message should be configured for the first Message Object.
User’s Manual TTCAN Revision 1.6 The Arbitration Registers (ID28-0 and Xtd bit) are given by the application. They define the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard Frame”) is used (Xtd = ‘0’), it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded. When a Data Frame with an 11-bit Identifier is received, ID17 - ID0 will be set to ‘0’. The Data Length Code (DLC3-0) is given by the application.
TTCAN User’s Manual Revision 1.6 ‘0’), it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded. When a Remote Frame with an 11-bit Identifier is received, ID17 - ID0 will be set to ‘0’. The Data Length Code (DLC3-0) may be given by the application. When the Message Handler stores a Remote Frame in the Message Object, it will store the received Data Length Code. The data bytes of the Message Object will remain unchanged.
TTCAN User’s Manual Revision 1.6 The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt. When no interrupt is pending, the register will hold the value zero. If the value of the Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set, the interrupt line to the CPU is active. The interrupt line remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
TTCAN User’s Manual Revision 1.6 4.3.3 Changing a Transmit Object In an application for that the number of Message Objects in the TTCAN module is not sufficient, the Transmit Objects may be managed dynamically. The CPU writes the whole message (Arbitration, Control, and Data) into the Interface Register. The Command Mask Register is set to 0x00B7 for the transfer of the contents into the designated Message Object. Neither MsgVal nor TxRqst have to be reset before this operation.
User’s Manual TTCAN START Revision 1.6 Message Interrupt Read Interrupt Pointer 0x8000h case Interrupt Pointer else 0x0000h Status Change Interrupt Handling END IFx Command Mask = 0x007F MessageNum = Interrupt Pointer Write MessageNum to IFx Command Request (Transfer Message to IFx Registers, Clear NewDat and IntPnd) Read IFx Message Control No NewDat = 1 Yes manual_about.
TTCAN User’s Manual Revision 1.6 5. TTCAN Application 5.1 TTCAN Configuration The TTCAN’s default operating mode after hardware reset is Standard CAN Communication without time triggers. The TTMode has to be switched into Configuration Mode before the timing and system matrix setup can be written into the TTCAN’s configuration registers. It is required that both Init and CCE are set before TTMode can be changed. 5.1.1 TTCAN Timing The Network Time Unit (NTU) is the unit in which all times are measured.
User’s Manual TTCAN TUR 8 10 24 50 510 Revision 1.6 125000 32.5 100/12 529/17 NumCfg 0x1FFF8 0x1FFFE 0x1FFF8 0x1FFEA 0x1FFFE 0x1E848 0x1FFE0 0x19000 0x10880 DenomCfg 0x3FFF 0x3333 0x1555 0x0A3D 0x0101 0x0001 0x0FC0 0x3000 0x0880 Figure 18: TUR configuration examples The TTCAN module provides a watchdog to verity the function of the application program. The host has to serve this watchdog regularly, else all CAN bus activity is stopped.
TTCAN User’s Manual Revision 1.6 operates according to ISO 11898-4, but without the possibility to synchronise the Basic Cycles to external events, the Next_is_Gap bit in the Reference Message is ignored. In the TTMode “Event Synchronised Time Triggered Operation”, the TTCAN module operates according to ISO 11898-4, including the event synchronised start of a Basic Cycle. ETT in the Matrix Limits registers specifies the number of Expected Tx_Triggers in the System Matrix.
TTCAN User’s Manual Revision 1.6 for Arbitrating Time Windows, Tx_Trigger_Merged may be used only for Merged Arbitrating Time Windows. The last Tx_Trigger of a Merged Arbitrating Time Window must be of the type Tx_Trigger_Single. A Configuration Error (Error level 3) is detected when a Trigger of the type Tx_Trigger_Merged is followed by any other Trigger than one of the type Tx_Trigger_Single or Tx_Trigger_Merged. Several Tx_Triggers may be defined for the same Message Object.
TTCAN User’s Manual Revision 1.6 A typical Trigger List for a potential Time Master will begin with a number of Tx_Triggers and Rx_Triggers followed by the Tx_Ref_Trigger and the Watch_Trigger. For networks with Event Synchronised Time triggered Communication, this is followed by the Tx_Ref_Trigger_Gap and the Watch_Trigger_Gap. The Trigger List for a Time Slave will be the same but without the Tx_Ref_Trigger and the Tx_Ref_Trigger_Gap.
TTCAN User’s Manual Revision 1.6 TxRqst and RmtEn may never be set for a periodic transmit message. To enable the transmission of a periodic message inside an Exclusive Time Window, TxRqst has to be set to ‘0’ and NewDat has to be set to ‘1’. The message will be transmitted each time its Tx_Trigger(s) become(s) active, neither TxRqst nor NewDat will be changed. MSC will be updated according to the success of the transmissions.
TTCAN User’s Manual Revision 1.6 reset or configuration, giving no acknowledge). When it reaches Initial_Watch_Trigger (not part of the Trigger List, defined as maximum of Cycle Time), the attempted transmission is aborted, IWT in the Interrupt Vector register is set, the FSE is frozen, and the Cycle Time will become invalid, but the node will still be able to take part in CAN bus communication (to give acknowledge or to send error flags).
TTCAN User’s Manual Revision 1.6 Window, the retransmission may happen inside the same Window. The retransmission will not be started if NewDat is reset by the application program. When a Message Object for event driven messages is managed dynamically, the contents of a Message Object may be changed at the same time the transmission is requested. In that case, any previous content of the Message Object that is not transmitted successfully is lost. 5.
User’s Manual TTCAN Revision 1.6 (the “Micro Tick”) is incremented eight times each NTU, or, when TUR becomes <8 by drift compensation or by configuration for TTCAN Level 1, it is incremented four times each NTU. Figure 19 describes the synchronisation of the Cycle Time and Global Time, performed in the same manner by all TTCAN nodes, including the Time Master. Any message received or transmitted invokes a capture of the Local Time taken at the message’s Frame Synchronisation Event.
User’s Manual TTCAN Reference Message actual Master_Ref_Mark previous Master_Ref_Mark Sync_Mark actual Ref_Mark ? = 1 ÷ Calibration of Time Unit Ratio previous Ref_Mark Start of Basic Cycle Revision 1.6 Figure 20: TTCAN Level 2 Drift Compensation Figure 20 describes how in TTCAN Level 2 each time receiving node compensates the drift between its own local clock and the Time Master’s clock by comparing the length of a Basic Cycle in Local Time and in Global Time.
User’s Manual TTCAN Revision 1.6 The TT Interrupt Vector consists of four segments, each four bits long. Each of the bits of the TT Interrupt Vector can be separately enabled by a corresponding bit in the TT Interrupt Enable register. Once a bit of the TT Interrupt Vector is set, it will remain set until the application program writes a ‘0’ to this bit. The first segment consists of CfE, ApW, Wtr, and IWT. Each of these interrupts indicates a fatal error condition where the CAN communication is stopped.
User’s Manual TTCAN Revision 1.6 The general configuration of the three nodes is identical, there are differences in the Operation Mode, the TT Matrix Limits, the Message RAM, and the Trigger Memory. Note that the CPU has to wait after each write access to the IF1 Command Request Register for the requested transfer to be completed (check of Busy bit). manual_about.
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User’s Manual TTCAN Line Ad 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 24 0E 22 24 0E 22 24 0E 22 24 0E 22 24 0E 22 24 0E 22 24 0E 66 28 00 Register IF1 Message Data B2 Trigger Memory Access IF1 Message Data B1 IF1 Message Data B2 Trigger Memory Access IF1 Message Data B1 IF1 Message Data B2 Trigger Memory Access IF1 Message Data B1 IF1 Message Data B2 Trigger Memory Access IF1 Message Data B1 IF1 Message Data B2 Trigger Memory Access IF1 Message Data B1 IF1 Message Data B2 Tri
TTCAN User’s Manual Revision 1.6 The transmit message objects 5…6, to be transmitted in the arbitrating time windows, may be controlled dynamically or may be restricted to specific messages. Their identifiers should have a lower priority than the Reference Message or the periodic messages.
User’s Manual TTCAN Revision 1.6 6. CPU Interface The interface of the TTCAN module consist of two parts (see figure 21). The Generic Interface which is a fixed part of the TTCAN module and the Customer Interface which can be adapted to the customers requirements.
User’s Manual TTCAN Revision 1.6 6.2 Timing of the WAIT output signal If the Customer Interfaces is implemented with a wait-function, the CPU is halted while a message transfer is in progress between the IFx Registers and the Message RAM, when the module’s optional output port CAN_WAIT_B is at active low level. Figure 22 shows the timing of CAN_WAIT_B with respect to the modules internal clock CAN_CLK.
User’s Manual TTCAN Revision 1.6 7. Appendix 7.1 List of Figures Figure 1: Block Diagram of the TTCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2: CAN_Core in Silent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3: CAN_Core in Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4: CAN_Core in Loop Back combined with Silent Mode . . . . . . . . . . . .
