Information

BNO055

Data sheet

Page 92

BST-BNO055-DS000-14 | Revision 1.4 | June 2016 Bosch Sensortec

to third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.

Note: Specifications within this document are subject to change without notice.

Figure 5: I²C timing diagram shows the definition of the I²C timings given in Table 4-8:

Figure 5: I²C timing diagram

The I²C protocol works as follows:

START: Data transmission on the bus begins with a high to low transition on the SDA line

while SCL is held high (start condition (S) indicated by I²C bus master). Once the START

signal is transferred by the master, the bus is considered busy.

STOP: Each data transfer should be terminated by a Stop signal (P) generated by master.

The STOP condition is a low to HIGH transition on SDA line while SCL is held high.

ACK: Each byte of data transferred must be acknowledged. It is indicated by an

acknowledge bit sent by the receiver. The transmitter must release the SDA line (no pull

down) during the acknowledge pulse while the receiver must then pull the SDA line low so

that it remains stable low during the high period of the acknowledge clock cycle.

In the following diagrams these abbreviations are used:

S Start

P Stop

ACKS Acknowledge by slave

ACKM Acknowledge by master

NACKM Not acknowledge by master

RW Read / Write

A START immediately followed by a STOP (without SCL toggling from ´VDDIO´ to ´GND´) is

not supported. If such a combination occurs, the STOP is not recognized by the device.

I²C write access:

I²C write access can be used to write a data byte in one sequence. The sequence begins

with start condition generated by the master, followed by 7 bits slave address and a write bit

(RW = 0). The slave sends an acknowledge bit (ACK = 0) and releases the bus. Then the

master sends the one byte register address. The slave again acknowledges the transmission

HDDAT

BUF

SDA

SCL

SDA

LOW

HDSTA

SUSTA

HIGH

SUDAT

SUSTO