Specifications

Data sheet
BMA220
Page 48
BST-BMA220-DS003-08 | Revision 1.15 | August 2011 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
7.4 I²C watchdog timer
In order to prevent the built-in I²C slave to lock-up the I²C bus, a watchdog timer (WDT) is
introduced. The WDT observes internal I²C signals and resets the I²C interface if the bus is
locked-up by the BMA220.
The WDT observation period and WDT on/off can be configured through interface registers.
Figure 24: WDT settings
WDT_TO_en WDT_TO_sel WDT function
0 X OFF
1 0 1 ms
1 1 10 ms
7.5 SPI and I²C access restrictions
The required wait time after a write-cycle depends on whether the power-saving (sleep) mode is
currently active. In case the low-power mode is active, the internal clock frequency is reduced
and thus the required wait time increases.
Table 23: Required wait times after write / before read access
Protocol Access Normal mode Low-power mode
I
2
C / SPI Write >3μsec >300μsec
I
2
C / SPI Read >2μsec >2μsec
Figure 25: Post-write access timing constraints
Figure 26: Pre-read access timing constraints
Please note that this read-constraint only applies to read-outs of the same axes. Reading
out the three axes in a back-to-back transfer is possible!