User manual

VETTA Theory of Operation………………Line 6 confidential ……………………………. Page 9 of 18
Clock system:
Except when the digital I/O option board is used (currently not available), all the clocks are
contained within the Main PCB.
There are two master clocks: CLK_30 (30MHz) and CLK_40 (40MHz).
The crystal oscillator Y3 generates the CLK_30 clock. Its only purpose is to set the execution
speed of the two Sharc DSP U35 and U36.
The crystal oscillator Y1 generates the CLK_40 clock. It has a number of distinct functions:
1). It sets the execution speed of the microprocessor U27 and drives all its peripheral access
timing through the PLD U28.
2) It provides the run rate for the MIDI and FBX interface (internally generated in U27).
3) After being divider by four by the flip-flop U32 it becomes the 256FS_CLK (10MHz) which
is the master clock for the audio sample rate. U17 implements a two-way switch, which allows
for using an alternate clock generated on a future digital I/O option card. This card is not
currently available and the switch should always be set to the U32 divider branch (= the
SEL_LOCAL/OPTION* control signal should remain high). The 256FS_CLK drives the
CODEC U16, which generates the FS-CLK (256FS_CLK/256= 39.0625KHz) and the
64FS_CLK (FS_CLK * 64 = 2.5MHz) signals. After buffering by U34 the 256FS_CLKB,
64FS_CLKB1, and FS_CLKB1 clocks drive the guitar input ADC U19 and the direct and
power amp output ADC U21 and U20. Also, after buffering by U3, the 64FS_CLKB2, and
FS_CLKB2 drive the DSP #1 and #2 to synchronize the DSP processing with the converters
sample rate.