User manual

VETTA Theory of Operation………………Line 6 confidential ……………………………. Page 11 of 18
Bus system:
DSP #1 U35 and #2 U36 share a common 32 bit wide data bus named DSP_DATA[00:31] and
a 24 bit wide address bus named DSP_ADDR[00:23]. These buses allow for communication
between the DSPs and with the SDRAM. The SDRAM can be configured either with two
1Meg. by 16 ICs (U37 and U38) or two 4 Meg. by 16 ICs (U39 and U40). The current Main
board is stuffed with U37 and U38 (1Meg.) (U39 and U40 are not installed on the PCB). Since
each SDRAM IC is only 16 bit data wide they each carry only half of the DSP data bus. U37
and U38 are accessed together as a single 1 Meg by 32 bit wide SDRAM with U37 carrying
the 16 less significant bits and U38 carrying the 16 most significant bits. These two busses also
permit communication between the DSPs and the microprocessor U27. The address bus lower
10 bits [00:09] can be driven by the microprocessor through the tri-state gate U41. The lower
16 bit of the data bus [00:15] can be bidirectionaly connected to the microprocessor address
bus through the bidirectional buffer U42. This interface permits to move the DSP code from
the microprocessor flash memory U26 into the DSP memory upon power on initialization. It
also permits to send new parameters to the DSP when a new patch is recalled or a U.I. control
is changed. This interface must be working for the DSP to run valid code after power on.
On the microprocessor side, the 32-bit data bus is called HOST_D[00:31], and the 24-bit
address bus is HOST_A[00:21] (bit 22 and 23 are not used). Through these buses the
microprocessor can access the FLASH memory U26 that holds the microprocessor and DSP
code. The data to the FLASH is bidirectional allowing the microprocessor to transfer new code
from MIDI to the FLASH thus allowing reprogramming the VETTA software operations from
the outside. These buses also connect to the SRAM U29, which is permanently supplied by a
battery, and hold the user defined data setups.
Finally, to allow bidirectional communication with the U.I. PCB, bit 24 to 32 of the data bus
are bidirectionaly buffered by U30 to the U.I. bus FB_D[00:07]. U31 buffers the 3 less
significant bits of the address bus.