Installation manual

Revision F • 3/12
HARRIS CORPORATION
2-6
2 Hardware Installation
the Fostex 6301D. It can alternately be used as a
source for a balanced AES-3, 44.1 kHz master
sample clock signal.
Pins 2 and 3 of each digital input and output
are fully protected against static (ESD), overvolt-
age spikes (EFT), and lightning surges. Pin 1 and
the XLR shell are tied directly to chassis ground.
If the HDE-200 power is lost, the
Main Delay
In
signal is relay switched to directly connect to
the
Main Delay Out connector for uninterrupted
operation.
When power is applied, it takes about one
minute for the HDE-200 to begin transmitting the
HD Radio data stream again. The
Main Delay Out
signal will automatically start to rebuild its Diver-
sity Delay about 30 seconds after power is ap-
plied. The method used to rebuild the Diversity
Delay is set using the ECC app’s System > Other
Controls pop-up window.
2.3.4 HDE-200 SAMPLE & BIT RATE
The HDE-200 uses a 44.1 kHz sample rate for
internal signal processing. The sample clock is
synchronized with a time-based signal obtained
from an internal GPS receiver. This ensures
sample-accurate synchronization with the HD
Radio Exciter.
The
44.1 kHz clock output (75 ohm BNC) is
typically tied to the HD Radio Importer in order
to synchronize it with the HDE-200 Exporter.
The
Ref Mon Out output (a female XLR con-
nector) can also be used as a 44.1 kHz master
sample clock output source.
All digital inputs (
Main Delay In , MPS Audio
In
and the two Post Delay Loop inputs) use built-
in sample rate conversion. Signals with sample
rates between 32 and 96 kHz and with bit depths
of 16- or 24-bits can be received. Bit depth is trun-
cated to 16-bits internally in the HDE-200.
Note that sample rate and bit depth conver-
sion cannot be bypassed in the HDE-200.
All digital outputs (
Main Delay Out , Ref Mon
Out
, the HD Radio data stream and the two Post
Delay Loop
outputs) use a 44.1 kHz sample rate
that is time-synchronized using the GPS System
clock signals. The HDE-200 outputs a 24-bit word,
which is using the 16 most significant bits.
2.3.5 S/PDIF CONNECTIONS
Digital devices with S/PDIF unbalanced out-
puts can connect to an HDE-200 input by tying
pins 1 and 3 together to unbalanced the input.
When a longer cable (beyond about fifteen feet)
is used, a 249 ohm terminating resistor may be
required to impedance match the S/PDIF cable
(which is typically 75-ohm coax cable) to the 110
ohm input. For shorter cables (under about fif-
teen feet), the terminating resistor is typically not
required. Solder the resistor onto the male XLR
terminals, per the following illustration.
An unbalanced-to-balanced line transformer can
alternately be used to interface a S/PDIF signal
to an AES-3 input.
To connect an HDE-200 output to an S/PDIF
input requires a voltage divider be used to lower
the AES-3 signal level to a level the S/PDIF input
can handle (shown in the diagram on the next
page).
Note: Some S/PDIF devices may not
interface correctly with the HDE-
200—even after adding resistors or
Connecting an S/PDIF Device to an
HDE-200 AES/EBU Input
1
3
2
+
-
* 249 ohm termination resistor
required if signal drops outs are
encountered (typically only used
with long cable runs)
Signal
Shield
HDE-200
XLR Input
Coax from the
S/PDIF Device
*