Datasheet

8
Table 6. Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
The following specifications cover the following power supply combinations: (4.5V≤V
DD1
≤5.5V, 4.5V≤V
DD2
≤5.5V),
(3V≤V
DD1
≤3.6V, 3V≤V
DD2
≤3.6V), (4.5V≤V
DD1
≤5.5V, 3V≤V
DD2
≤3.6V) and (3V≤V
DD1
≤3.6V, 4.5V≤V
DD2
≤5.5V).
All typical specifications are at T
A
=+25°C, V
DD1
= V
DD2
= +3.3V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Propogation Delay Time to Logic Low Output
[3]
t
PHL
23.5 40 ns C
L
= 15 pF, CMOS Signal Levels
Propogation Delay Time to Logic High Output
[3]
t
PLH
25.5 40 ns C
L
= 15 pF, CMOS Signal Levels
Pulse Width
[4]
t
PW
40 ns C
L
= 15 pF, CMOS Signal Levels
Maximum Data Rate
[5]
25 MBd C
L
= 15 pF, CMOS Signal Levels
Pulse Width Distortion
[6]
| t
PHL
- t
PLH
| |PWD | 2 6 ns C
L
= 15 pF, CMOS Signal Levels
Propagation Delay Skew
[7]
t
PSK
20 ns C
L
= 15 pF, CMOS Signal Levels
Output Rise Time (10% – 90%) t
R
9 ns C
L
= 15 pF, CMOS Signal Levels
Output Fall Time (90% - 10%) t
F
8 ns C
L
= 15 pF, CMOS Signal Levels
Common Mode Transient Immunity at Logic High Output
[8]
| CM
H
| 10 20
kV/ms
V
CM
= 1000 V, T
A
= 25°C,
V
I
= V
DD1
, V
O
> 0.8 V
DD1
Common Mode Transient Immunity at Logic Low Output
[8]
| CM
L
| 10 20
kV/ms
V
CM
= 1000 V, T
A
= 25°C,
V
I
= 0 V, V
O
< 0.8 V
Table 7. Package Characteristics
All typical specifications are at T
A
= 25°C.
Parameters Symbol Min. Typ. Max. Units Test Conditions
Input-Output Momentary
With-stand Voltage
[7,8,9]
072L V
ISO
3750 V rms RH ≤ 50%, t = 1 min, T
A
= 25°C
772L 3750
772L with
020 option
5000
Input-Output Resistance
[9]
R
I-O
10
12
W
V
I-O
= 500 V dc
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz
Input Capacitance
[12]
C
I
3.0 pF
Input IC Junction-to-Case
Thermal Resistance
772L
qjci
145 °C/W Thermocouple located at center underside of package
072L 160
Output IC Junction-to-Case
Thermal Resistance
772L
qjco
140 °C/W
072L 135
Package Power Dissipation P
PD
150 mW
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when V
I
is low and OFF when V
I
is high.
3. t
PHL
propagation delay is measured from the 50% level on the falling edge of the V
I
signal to the 50% level of the falling edge of the V
O
signal. t
PLH
propagation delay is measured from the 50% level on the rising edge of the V
I
signal to the 50% level of the rising edge of the V
O
signal.
4. The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
5. The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
6. PWD is defined as |t
PHL
- t
PLH
|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
7. t
PSK
is equal to the magnitude of the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within the
recommended operating conditions.
8. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining V
O
< 0.8 V. The common mode voltage slew rates apply to both rising and falling
common mode voltage edges.
9. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.