Datasheet
13
Applications Information
Eliminating Negative IGBT Gate Drive ACPL-312T
To keep the IGBT rmly o, the ACPL-312T has a very low
maximum V
OL
specication of 0.5 V. The ACPL-312T real-
izesthis very low V
OL
by using a DMOS transistor with 1 Ω
(typical) on resistance in its pull down circuit. When the
ACPL-312T is in the low state, the IGBT gate is shorted to
the emitter by Rg + 1 Ω. Minimizing Rg and the lead induc-
tance from the ACPL-312T to the IGBT gate and emitter
(possibly by mounting the ACPL-312T on a small PC board
directly above the IGBT) can eliminate the need for nega-
Figure 25. Recommended LED drive and application circuit.
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses.
Step 1: Calculate Rg Minimum from the I
OL
Peak Speci-
cation. The IGBT and Rg in Figure 26 can be analyzed as
a simple RC circuit with a voltage supplied by the HCPL-
3120.
OLPEAK
OLEECC
g
I
VVV
R
)( −−
≥
OLPEAK
EECC
I
VVV )2( −−
=
A5.2
)2515( −+
=
Ω≅Ω= 82.7
g
R
The V
OL
value of 2 V in the previous equation is a conser-
vative value of VOL at the peak current of 2.5A (see Figure
6). At lower Rg values the voltage supplied by the ACPL-
312T is not an ideal voltage step. This results in lower peak
currents (more margin) than predicted by this analysis.
When negative gate drive is not used VEE in the previous
equation is equal to zero volts.
tive IGBT gate drive in many applications as shown in Fig-
ure 25. Care should be taken with such a PC board design
to avoid routing the IGBT collector or emitter traces close
to the ACPL-312T input as this can result in unwanted cou-
pling of transient signals into the ACPL-312T and degrade
performance. (If the IGBT drain must be routed near the
ACPL-312T input, then the LED should be reverse-biased
when in the o state, to prevent the transient signals cou-
pled from the IGBT drain from turning on the ACPL-312T).
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF
V
CC
= 18 V
1
3
+
–
2
4
8
6
7
5
270Ω
ACPL-312T
+5V
CONTROL
INPUT
Rg
Q1
Q2
CMOS
DRIVER
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF
V
CC
= 15 V
1
3
+
–
2
4
8
6
7
5
Rg
Q1
Q2
V
EE
= -5 V
–
+
270Ω
+5V
CONTROL
INPUT
CMOS
DRIVER
Figure 26. ACPL-312T typical application circuit with negative IGBT gate drive.