Datasheet

16
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5V
+
–
V
CC
= 18 V
ttt
ttt
0.1
µF
+
–
–
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5V
Q1
I
LEDN
CMR with the LED On (CMRH).
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriv-
ing the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient. A
minimum LED current of 10 mA provides adequate mar-
gin over the maximum IFLH of 5 mA to achieve 25 kV/μs
CMR. CMR with the LED O (CMRL). A high CMR LED drive
circuit must keep the LED o (V
F
≤ V
F(OFF)
) during com-
mon mode transients. For example, during a -dV
cm
/dt
transient in Figure 31, the current owing through C
LEDP
also ows through the R
SAT
and V
SAT
of the logic gate. As
Figure 31. Equivalent circuit for gure 25 during common mode transient.
Figure 32. Not recommended open collector drive circuit.
Figure 33. Recommended LED drive circuit for ultra-high CMR.
long as the low state voltage developed across the logic
gate is less than V
F(OFF)
, the LED will remain o and no
common mode failure will occur. The open collector drive
circuit, shown in Figure 32, cannot keep the LED o during
a +dV
cm
/dt transient, since all the current owing through
C
LEDN
must be supplied by the LED, and it is not recom-
mended for applications requiring ultra high CMRL per-
formance. Figure 33 is an alternative drive circuit which,
like the recommended application circuit (Figure 25), does
achieve ultra high CMR performance by shunting the LED
in the o state.