Datasheet
22
Figure 38. Output pull-down resistor.
Under Voltage Lockout
The ACPL-332J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insucient gate
voltage to the IGBT by forcing the ACPL-332J output
low during power-up. IGBTs typically require gate
voltages of 15 V to achieve their rated V
CE(ON)
voltage.
At gate voltages below 13 V typically, the V
CE(ON)
voltage
increases dramatically, especially at higher currents. At
very low gate voltages (below 10 V), the IGBT may operate
in the linear region and quickly overheat. The UVLO
function causes the output to be clamped whenever in-
sucient operating supply (V
CC2
) is applied. Once V
CC2
exceeds V
UVLO+
(the positive-going UVLO threshold), the
UVLO clamp is released to allow the device output to turn
on in response to input signals. As V
CC2
is increased from
0 V (at some level below V
UVLO+
), rst the DESAT protec-
tion circuitry becomes active. As V
CC2
is further increased
(above V
UVLO+
), the UVLO clamp is released. Before the
time the UVLO clamp is released, the DESAT protection
is already active. Therefore, the UVLO and DESAT Fault
detection feature work together to provide seamless pro-
tection regardless of supply voltage (V
CC2
).
Active Miller Clamp
A Miller clamp allows the control of the Miller current
during a high dV/dt situation and can eliminate the use
of a negative supply voltage in most of the applications.
During turn-o, the gate voltage is monitored and the
clamp output is activated when gate voltage goes below
2V (relative to V
EE
). The clamp voltage is V
OL
+2.5V typ
for a Miller current up to 1100mA. The clamp is disabled
when the LED input is triggered again.
Other Recommended Components
The application circuit in Figure 36 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor, and a FAULT pin pullup resistor and
Active Miller Clamp connection.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of V
CC2
. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly V
CC2
-3(V
BE
)
to V
CC2
within a period of several microseconds. To limit
the output voltage to V
CC2
-3(V
BE
), a pull-down resistor,
R
PULL-DOWN
between the output and V
EE
is recommended
to sink a static current of several 650 µA while the output
is high. Pull-down resistor values are dependent on the
amount of positive supply and can be adjusted according
to the formula, R
pull-down
= [V
CC2
-3 * (V
BE
)] / 650 µA.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
R
G
R
PULL-DOWN
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
R
G
R
PULL-DOWN
V
CC
DESAT Pin Protection Resistor
The freewheeling of yback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substan-
tial current out of the driver if protection is not used. To
limit this current to levels that will not damage the driver
IC, a 100 ohm resistor should be inserted in series with
the DESAT diode. The added resistance will not alter the
DESAT threshold or the DESAT blanking time.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
R
G
V
CC
100 Ω
100pF
D
DESAT
Figure 39. DESAT pin protection.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can aect the fault pin
voltage while the fault output is in the high state. A 330
pF capacitor should be connected between the fault pin
and ground to achieve adequate CMOS noise margins at
the specied CMR value of 15 kV/µs. The added capaci-
tance does not increase the fault output delay when a
desaturation condition is detected.