Datasheet

9
Table 7. Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage
V
ISO
3750 V
rms
RH < 50%, t = 1 min.,
T
A
= 25°C
6, 7
Input-Output Resistance R
I-O
> 10
9
W
V
I-O
= 500 V 7
Input-Output Capacitance C
I-O
1.3 pF freq=1 MHz
Output IC-to-Pins 9 &10
Thermal Resistance
q
09-10
30 °C/W T
A
= 25°C
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. In order to achieve the absolute maximum power dissipation specied, pins 4, 9, and 10 require ground plane connections and may require
airow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air ow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with I
O
peak minimum = 2.0 A. Derate
linearly from 3.0 A at +25°C to 2.5 A at +100°C. This compensates for increased I
OPEAK
due to changes in V
OL
over temperature.
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 µs.
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (V
CC2
- V
E
) to ensure adequate margin in excess of the maximum V
UVLO+
threshold of 12.5V. For High Level Output Voltage testing, V
OH
is measured with a dc load current. When driving capacitive loads, V
OH
will
approach V
CC
as I
OH
approaches zero units.
8. Maximum pulse width = 1.0 ms.
9. Once V
O
of the ACPL-332J is allowed to go high (V
CC2
- V
E
> V
UVLO
), the DESAT detection feature of the ACPL-332J will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
UVLO+
> 12.5 V, DESAT will remain functional until V
UVLO-
< 9.2 V. Thus, the
DESAT detection and UVLO features of the ACPL-332J work in conjunction to ensure constant IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the “increasing” (i.e. turn-on or “positive going” direction) of V
CC2
- V
E
12. This is the “decreasing” (i.e. turn-o or “negative going” direction) of V
CC2
- V
E
13. This load condition approximates the gate load of a 1200 V/150A IGBT.
14. Pulse Width Distortion (PWD) is dened as |t
PHL
- t
PLH
| for any given unit.
15. As measured from I
F
to V
O
.
16. The dierence between t
PHL
and t
PLH
between any two ACPL-332J parts under the same test conditions.
17. As measured from ANODE, CATHODE of LED to V
OUT
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before V
OUT
begins to go low, and the FAULT output to go low. This is supply
voltage dependent.
20. Auto Reset: This is the amount of time when V
OUT
will be asserted low after DESAT threshold is exceeded. See the Description of Operation (Auto
Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the
output will remain in the high state (i.e., V
O
> 15 V or FAULT > 2 V). A 100 pF and a 2.1 kΩ pull-up resistor is needed in fault detection mode.
22. Common mode transient immunity in the low state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the
output will remain in a low state (i.e., V
O
< 1.0 V or FAULT < 0.8 V).
23. To clamp the output voltage at V
CC
- 3 V
BE
, a pull-down resistor between the output and V
EE
is recommended to sink a static current of 650 µA
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.