Datasheet

7
AC Timing Characteristics Over Temperature Range (-40 °C to +85 °C)
Timing
Diagram Ref. 4.5 V < V
LOGIC
<5.5 V V
LOGIC
= 3 V
Number Description Symbol Min. Max. Min. Max. Units
1 Register Select Setup Time to Chip Enable t
rss
10 10 ns
2 Register Select Hold Time to Chip Enable t
rsh
10 10 ns
3 Rising Clock Edge to Falling t
clkce
20 20 ns
Chip Enable Edge
4 Chip Enable Setup Time to Rising Clock Edge t
ces
35 55 ns
5 Chip Enable Hold Time to Rising Clock Edge t
ceh
20 20 ns
6 Data Setup Time to Rising Clock Edge t
ds
10 10 ns
7 Data Hold Time after Rising Clock Edge t
dh
10 10 ns
8 Rising Clock Edge to D
OUT
[1]
t
dout
10 40 10 65 ns
9 Propagation Delay D
IN
to D
OUT
t
doutp
18 30 ns
Simultaneous Mode for One IC
[1,2]
10 CE Falling Edge to D
OUT
Valid t
cedo
25 45 ns
11 Clock High Time t
clkh
80 100 ns
12 Clock Low Time t
clkl
80 100 ns
Reset Low Time t
rstl
50 50 ns
Clock Frequency F
cyc
5 4 MHz
Internal Display Oscillator Frequency F
inosc
80 210 80 210 kHz
Internal Refresh Frequency F
rf
150 410 150 400 Hz
External Display Oscillator Frequency F
exosc
Prescaler = 1 51.2 1000 51.2 1000 kHz
Prescaler = 8 410 8000 410 8000 kHz
Notes:
1. Timing specications increase 0.3 ns per pF of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.