Datasheet
6
Electrical Description
Pin Function Description
RESET (RST) Sets Control Register bits to logic low. The Dot Register contents are unaected by the Reset pin.
(logic low = reset; logic high = normal operation).
DATA IN (D
IN
) Serial Data input for Dot or Control Register data. Data is entered on the rising edge of the Clock input.
DATA OUT (D
OUT
) Serial Data output for Dot or Control Register data. This pin is used for cascading multiple displays.
CLOCK (CLK) Clock input for writing Dot or Control Register data. When Chip Enable is logic low, data is entered on the
rising Clock edge.
REGISTER SELECT (RS) Selects Dot Register (RS = logic low) or Control Register (RS = logic high) as the destination for serial data
entry. The logic level of RS is latched on the falling edge of the Chip Enable input.
CHIP ENABLE (CE) This input must be a logic low to write data to the display. When CE returns to logic high and CLK is logic
low, data is latched to either the LED output drivers or a Control Register.
OSCILLATOR SELECT Selects either an internal or external display oscillator source. (SEL) (logic low = External Display
Oscillator; logic high = Internal Display Oscillator).
OSCILLATOR (OSC) Output for the Internal Display Oscillator (SEL = logic high) or input for an External Display Oscillator
(SEL = logic low).
BLANK (BL) Blanks the display when logic high. May be modulated for brightness control.
GND
LED
Ground for LED drivers.
GND
LOGIC
Ground for logic.
V
LED
Positive supply for LED drivers.
V
LOGIC
Positive supply for logic.
AC Timing Characteristics over Temperature Range (-40 to +85° C)
Timing
Diagram
Ref. Number Description Symbol
4.5 V<V
LOGIC
< 5.5 V V
LOGIC
= 3 V
UnitsMin. Max. Min. Max.
1 Register Select Setup Time to Chip Enable t
rss
10 10 ns
2 Register Select Hold Time to Chip Enable t
rsh
10 10 ns
3 Rising Clock Edge to Falling Chip Enable Edge t
clkce
20 20 ns
4 Chip Enable Setup Time to Rising Clock Edge t
ces
35 55 ns
5 Chip Enable Hold Time to Rising Clock Edge t
ceh
20 20 ns
6 Data Setup Time to Rising Clock Edge t
ds
10 10 ns
7 Data Hold Time after Rising Clock Edge t
dh
10 10 ns
8 Rising Clock Edge to D
OUT
[1]
t
dout
10 40 10 65 ns
9 Propagation Delay D
IN
to D
OUT
Simultaneous Mode for one IC
[1,2]
t
doutp
18 30 ns
10 CE Falling Edge to D
OUT
Valid t
cedo
25 45 ns
11 Clock High Time t
clkh
80 100 ns
12 Clock Low Time t
clkl
80 100 ns
Reset Low Time t
rstl
50 50 ns
Clock Frequency F
cyc
5 4 MHz
Internal Display Oscillator Frequency F
inosc
80 210 80 210 KHz
Internal Refresh Frequency F
rf
150 410 150 410 Hz
External Display Oscillator Frequency
Prescaler = 1
Prescaler = 8
F
exosc
51.2
410
1000
8000
51.2
410
1000
8000
KHz
KHz
Notes:
1. Timing specications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.