Datasheet

10
Figure 7. Pixel map
Control Register
The Control Register allows software modication of
the IC’s operation and consists of two independent 7-bit
control words. Bit D7 in the shift register selects one of the
two 7-bit control words. Control Word 0 performs pulse
width modulation Figure 7. Pixel map. brightness control,
peak pixel current brightness control, and sleep mode.
Control Word 1 sets serial/simultaneous data out mode,
and external oscillator prescaler. Each function is indepen-
dent of the others.
Control Register Data Loading
Data is loaded into the Control Register, MSB rst,
according to the procedure shown in Table 1 and Figure 5.
First, RS is brought to logic high and then CE is brought to
logic low. Next, each successive rising CLK edge will shift
in the data on the DIN pin. Finally, when 8 bits have been
loaded, the CE line is brought to logic high. When CLK goes
to logic low, new data is copied into the selected control
word. Loading data into the Control Register takes place
while the previous control word congures the display.
Control Word 0
Loading the Control Register with D
7
= Logic low selects
Control Word 0 (see Table 2). Bits D
0
-D
3
adjust the
display brightness by pulse width modulating the LED
on time, while Bits D
4
-D
5
adjusts the display brightness
by changing the peak pixel current. Bit D
6
selects normal
operation or sleep mode.
Sleep mode (Control Word 0, bit D
6
= Low) turns o the
Internal Display Oscillator and the LED pixel drivers. This
mode is used when the IC needs to be powered up, but
does not need to be active. Current draw in sleep mode
is nearly zero. Data in the Dot Register and Control Words
are retained during sleep mode.
Control Word 1
Loading the Control Register with D
7
= logic high selects
Control Word 1. This Control Word performs two functions:
serial/ simultaneous data out mode and external oscillator
prescale select (see Table 2).
ROW 0
(NOT USED)
DATA TO
NEXT
CHARACTER
PIXEL
DATA FROM
PREVIOUS
CHARACTER
ROW 7
ROW 6
ROW 5
ROW 4
ROW 3
ROW 2
ROW 1