Datasheet

3
Therefore, as the gate-to-emitter
voltage approaching zero, the
effect of anti-parallel diode
becomes less significant. Conse-
quently, turn-off delay time is
reduced, but improvement
switching times and dv/dt immu-
nity is only incremental.
B. PNP Turn-Off Speed Improvement
Circuit
One of the most popular arrange-
ments to improve turn-off speed
is the pnp turn-off speed
improvement circuit illustrated
in Figure 4.
In this simple circuit, during the
turn-on, the input capacitor of
IGBT is being charged through
gate resistor, R
GATE
and turn-on
diode, D
ON
. D
ON
also prevent
reverse breakdown of the base-
emitter junction of Q
OFF
during
the initial stage of the turn-on
process.
During turn-off, the pnp transis-
tor, Q
OFF
, is being turned-on, and
gate turn-off current is being dis-
charges through Q
OFF
to emitter
of IGBT. With this simple circuit
configuration, the area enclosed
by high turn-off discharge cur-
rent loop is being minimized.
The speed improvement circuit
minimizes ground-bouncing
problem by not discharging the
turn-off current through the gate
driver. Simultaneously, the
power dissipation of the gate
driver is cut to half.
C. Negative Gate Drive Turn-off
Speed Improvement Circuit
Low level output voltage, V
OL
of
HCPL-3020 and HCPL-0302 of
1.0V maximum possibly elimi-
nates the need to negative gate
drive for many applications.
Under certain circumstances, a
negative gate voltage as shown in
Figure 5 can be applied to
reduce the switching losses dur-
ing turn-off.
Negative gate drive also help to
ensure IGBTs in off state during
turn-off process even with the
present of high dv/dt noise in
collector-emitter voltage.
1
2
4
3
5
6
7
8
V
CC
R
GATE
D
OFF
1
2
4
3
5
6
7
8
V
CC
R
GATE
D
OFF
Figure 3. Anti-Parallel Diode Turn-Off Speed Improvement Circuit.
1
2
4
3
5
6
7
8
V
CC
R
GATE
D
ON
Q
OFF
1
2
4
3
5
6
7
8
V
CC
R
GATE
D
ON
Q
OFF
Figure 4. PNP Turn-Off Speed Improvement Circuit.
1
2
4
3
5
6
7
8
V
CC
V
EE
1
2
4
3
5
6
7
8
V
CC
V
EE
Figure 5. Negative Gate Drive (V
EE
) for Fast Turn-off.