Datasheet

Propagation delay skew represents the uncertainty of
where an edge might be after being sent through a digital
isolator. Figure 5 shows that there will be uncertainty in
both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider-
ations, the absolute minimum pulse width that can be
sent through digital isolators in a parallel application is
twice t
PSK
. A cautious design should use a slightly longer
pulse width to ensure that any additional uncertainty in
the rest of the circuit does not cause a problem.
Figure 6 shows the minimum pulse width, rise and fall
time, and propagation delay enable to output waveforms
for HCPL-9000 or HCPL-0900.
Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to Output Waveforms for HCPL-9000
or HCPL-0900.
50%
50%
90%
10% 10%
90%
V
IN
V
OUT
V
OE
t
PW
t
PLZ
t
PZH
t
PHZ
t
PZL
t
F
t
R
t
PW
Minimum Pulse Width t
PHZ
Propagation Delay, High to High Impedance
t
PLZ
Propagation Delay, Low to High Impedance t
PZL
Propagation Delay, High Impedance to Low
t
PZH
Propagation Delay, High Impedance to High t
R
Rise Time
t
F
Fall Time
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Data subject to change. Copyright © 2007 Avago Technologies, Limited. All rights reserved. Obsoletes 5989-0803EN
AV02-0137EN - November 27, 2007