Data Sheet

Broadcom AV02-0629EN
10
HDSP-210x/-211x/-250x Series Data Sheet Eight-Character 5 mm and 7 mm Smart Alphanumeric Displays
Figure 6: HDSP-210X/-211X/-212X/-250X Internal Block Diagram
Display Internal Block Diagram
Figure 6 shows the internal block diagram of the HDSP-210X/211X/-250X displays. The CMOS IC consists of an 8-byte
Character RAM, an 8-bit Flash RAM, a 128-character ASCII decoder, a 16-character UDC RAM, a UDC Address Register,
a Control Word Register, and the refresh circuitry necessary to synchronize the decoding and driving of eight 5×7 dot matrix
characters. The major user-accessible portions of the display are listed below:
Character RAM This RAM stores either ASCII character data or a UDC RAM address.
Flash RAM This is a 1×8 RAM which stores Flash data.
User-Defined Character RAM (UDC RAM) This RAM stores the dot pattern for custom characters.
User-Defined Character Address
Register (UDC Address Register)
This register is used to provide the address to the UDC RAM when the user is writing or
reading a custom character.
Control Word Register This register allows the user to adjust the display brightness, flash individual characters,
blink, self test, or clear the display.
A
3
A
4
FL
EN
UDC ADDR REGISTER
UDC
ADDR
RD
WR
D
0
-D
7
CLR
PRE SET
CE
A
3
A
4
A
0
-A
2
D
0
-D
7
FL
CE
WR
RD
A
3
A
4
FL
CE
FL
CE
A
3
A
4
FL
CE
A
3
A
4
FL
CE
EN
8 x 8
CHARACTER
RAM
D
0
-D
6
RD
WR
D
0
-D
7
A
0
-A
2
RESET
CHAR ADDR
D
7
EN
FLASH
RAM
FLASH
DATA
RD
WR
D
0
A
0
-A
2
RESET
CHAR ADDR
EN
UDC RAM
DOT
DATA
RD
WR
D
0
-D
4
D
0
-D
4
A
0
-A
2
UDC ADDR
ROW SET
EN
EN
ROW
SEL
SELF
TEST
ASCII
DECODER
DOT
DATA
D
0
-D
6
TIMING
TIMING
DOT
DRIVERS
DOT
DATA
EN
FLASH
CONTROL WORD
REGISTER
0
1
RD
WR
RST
CLK
OCS
CLS
CLR1
CLR2
D
0
-D
7
RESET
SELF TEST
RESULT
2
3
4
6
7
SELF
TEST
IN
SELF TEST
SELF TEST
SELF
TEST
START
8 5x7
LED
CHARACTERS
ROW DRIVERS
VISUAL
TEST
ROM
TEST
CLR
TEST OK
TEST OK
INTENSITY
INTENSITY
FLASH
FLASH
BLINK
BLINK
RESET
RESET
CLOCK
TIMING
AND
CONTROL
CHAR
ADDR
ROW SET
TIMING