Data Sheet

Broadcom AV02-0629EN
12
HDSP-210x/-211x/-250x Series Data Sheet Eight-Character 5 mm and 7 mm Smart Alphanumeric Displays
UDC RAM and UDC Address Register
Figure 8 shows the logic levels required to access the UDC RAM and the UDC Address Register. The UDC Address Register
is eight bits wide. The lower four bits (D
0
–D
3
) are used to select one of the 16 UDC locations. The upper four bits (D
4
–D
7
)
are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed.
To completely specify a 5×7 character, eight write cycles are required. One cycle is used to store the UDC RAM address in
the UDC Address Register and seven cycles are used to store dot data in the UDC RAM. Data is entered by rows and one
cycle is needed to access each row. Figure 9 shows the organization of a UDC character assuming the symbol to be stored
is an F. A
0
–A
2
are used to select the row to be accessed and D
0
–D
4
are used to transmit the row dot data. The upper three
bits (D
5
–D
7
) are ignored. D
0
(least significant bit) corresponds to the right most column of the 5×7 matrix and D
4
(most
significant bit) corresponds to the left most column of the 5×7 matrix.
Figure 8: Logic Levels to Access a UDC Character
CE
FL A
4
A
3
A
2
A
1
A
0
RST WR RD
01
00
01
1
001XXX
0
11
Undefined
Control Signals
UDC Address Register Address
UDC Address Register Data Format
Write to Display
Read from Display
Undefined
000 = Row 1
110 = Row 7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X UDC Code
XXX
FL A
4
A
3
A
2
A
1
A
0
011 Row Select
UDC RAM Address
UDC RAM C C
Data Format O O
L L
1 5
0 = Logic 0; 1 = Logic 1; X = Do Not Care
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X Dot Data
XX
CERST WR RD
01
00
01
10
11
Undefined
Control Signals
Write to Display
Read from Display
Undefined