Data Sheet

Table Of Contents

Broadcom AV02-0629EN

HDSP-210x/-211x/-250x Series Data Sheet Eight-Character 5 mm and 7 mm Smart Alphanumeric Displays

Self-Test Function (Bits 5, 6)

Bit 6 of the Control Word Register is used to initiate the self-test function. Results of the internal self test are stored in bit 5

of the Control Word. Bit 5 is a read only bit where bit 5 = 1 indicates a passed self test and bit 5 = 0 indicates a failed self test.

Setting bit 6 to a logic 1 starts the self-test function. The built-in self test function of the IC consists of two internal routines

which exercise major portions of the IC and illuminate all of the LEDs. The first routine cycles the ASCII decoder ROM

through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to 1.

The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered

and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds.

During the self test function the display must not be accessed. The time needed to execute the self test function is calculated

by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 kHz, then the time to execute the

self test function frequency is equal to (262,144/58,000) = 4.5 second duration.

At the end of the self test function, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except

for bit 5, the Flash RAM is cleared, and the UDC Address Register is set to all ones.

Clear Function (Bit 7)

Bit 7 of the Control Word clears the Character RAM and the Flash RAM. Setting bit 7 to a 1 starts the clear function. Three

clock cycles (110 ms minimum using the internal refresh clock) are required to complete the clear function. The display must

not be accessed while the display is being cleared. When the clear function has been completed, bit 7 resets to a 0. The

ASCII character code for a space (20H) loads into the Character RAM to blank the display and the Flash RAM loads with

0s. The UDC RAM, UDC Address Register, and the remainder of the Control Word are unaffected.

Display Reset

Figure 12 shows the logic levels needed to Reset the display. The display should be Reset on Power-up. The external Reset

clears the Character RAM, Flash RAM, Control Word, and resets the internal counters. After the rising edge of the Reset

signal, three clock cycles (110 μs minimum using the internal refresh clock) are required to complete the reset sequence.

The display must not be accessed while the display is being reset. The ASCII Character code for a space (20H) loads into

the Character RAM to blank the display. The Flash RAM and Control Word Register are loaded with all 0s. The UDC RAM

and UDC Address Register are unaffected. All displays that operate with the same clock source must be simultaneously

reset to synchronize the Flashing and Blinking functions.

Figure 12: Logic Levels to Reset the Display

CERST WR RD

0 = Logic 0; 1 = Logic 1; X = Do Not Care

Note: If RST, CE, and WR are low, unknown

data may be written into the display.

1XXXXX

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