Data Sheet
Table Of Contents
- Overview
- Features
- Applications
- Device Selection Guide
- Package Dimensions
- Absolute Maximum Ratings
- ASCII Character Set
- Recommended Operating Conditions
- Electrical Characteristics
- Optical Characteristics
- AC Timing Characteristics
- AC Timing Frequency Characteristics
- Electrical Description
- Display Internal Block Diagram
- Character RAM
- UDC RAM and UDC Address Register
- Flash RAM
- Control Word Register
- Brightness (Bits 0–2)
- Flash Function (Bit 3)
- Blink Function (Bit 4)
- Current Requirements at Different Brightness Levels (VDD = 5.0V)
- Self-Test Function (Bits 5, 6)
- Clear Function (Bit 7)
- Display Reset
- Mechanical and Electrical Considerations
- Thermal Considerations
- Ground Connections
- Thermal Resistance (θJA) Using Various Amounts of Heatsinking Material
- Soldering and Post Solder Cleaning Instructions for the HDSP-210X/- 211X/250X
- Contrast Enhancement
- Intensity Bin Limits for HDSP-2107
- Intensity Bin Limits for HDSP-211x and HDSP-250x (Except HDSP-2504)
- Intensity Bin Limit for HDSP-2504
- Color Bin Limits
- Packing Information
Broadcom AV02-0629EN
9
HDSP-210x/-211x/-250x Series Data Sheet Eight-Character 5 mm and 7 mm Smart Alphanumeric Displays
Electrical Description
Pin Function Description
Reset (RST, pin 1) Initializes the display.
Flash (FL
, pin 2) FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A
3
–A
4
.
Address Inputs (A
0
–A
4
,
pins 3–6, 10)
Each location in memory has a distinct address. Address inputs (A
0
–A
2
) select a specific location in the
Character RAM, the Flash RAM or a particular row in the UDC (User-Defined Character) RAM. A
3
–A
4
are
used to select which section of memory is accessed. The table below shows the logic levels needed to
access each section of memory.
Logic Levels to Access Memory
Clock Select (CLS, pin 11) Used to select either an internal (CLS = 1) or external (CLS = 0) clock source.
Clock Input/Output (CLK,
pin 12)
Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays.
Write (WR, pin 13) Data is written into the display when the WR input is low and the CE input is low.
Chip Enable (CE
, pin 17) Must be at a logic low to read or write data to the display and must go high between each read and write
cycle.
Read (RD, pin 18) Data is read from the display when the RD input is low and the CE input is low.
Data Bus (D
0
–D
7
, pins 19,
20, 23–28)
Used to read from or write to the display.
GND (SUPPLY) (pin 15) Analog ground for the LED drivers.
GND (LOGIC) (pin 16) Digital ground for internal logic.
VDD (POWER) (pin 14) Positive power supply input.
Section of Memory FL A4 A3 A2, A1, A0
Flash RAM 0 X X Character Address
UDC Address Register 1 0 0 Don’t Care
UDC RAM 1 0 1 Row Address
Control Word Register 1 1 0 Don’t Care
Character RAM 1 1 1 Character Address