Datasheet

8
Figure 1. HDSP-253X internal block diagram.
A
3
A
4
FL
EN
UDC ADDR REGISTER
UDC
ADDR
RD WR D
0
-D
7
CLR PRE SET
CE
A
3
A
4
A
0
-A
2
D
0
-D
7
FL
CE
WR
RD
A
3
A
4
FL
CE
FL
CE
A
3
A
4
FL
CE
A
3
A
4
FL
CE
EN
8 x 8
CHARACTER
RAM
D
0
-D
6
RD WR D
0
-D
7
A
0
-A
2
RESET CHAR ADDR
D
7
EN
FLASH
RAM
FLASH
DATA
RD WR D
0
A
0
-A
2
RESET CHAR ADDR
EN
UDC RAM
DOT
DATA
RD WR D
0
-D
4
D
0
-D
4
A
0
-A
2
UDC ADDR ROW SET EN EN ROW SEL SELF TEST
DECODER(*)
DOT
DATA
D
0
-D
6
TIMING
TIMING
DOT
DRIVERS
DOT DATA
EN
FLASH
CONTROL WORD
REGISTER
0 1
RD WR
RST
CLK
OCS
CLS
CLR1
CLR2
D
0
-D
7
RESET SELF TEST RESULT
2 3 4 6 7
SELF TEST IN
SELF TEST
SELF TEST
SELF TEST START
8 5x7
LED
CHARACTERS
ROW DRIVERS
VISUAL
TEST
ROM
TEST
CLR
TEST OK
TEST OK
INTENSITY
INTENSITY
FLASH
FLASH
BLINK
BLINK
RESET
RESET
CLOCK
TIMING
AND
CONTROL
CHAR
ADDR
ROW SET
TIMING