Specifications

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current level.
2. NRST is hardware reset for the module and will be effective with VIL. Configuration
information will be remained after module reset. The module is already designed with RC reset
upon power-on.
3. The pins for reset button and LED indication should be defined according to actual
firmware and circuit design.
4. In default, PIN11 (GPIO2) is the module software reset PIN and will be effective with
VIH. The previous configuration information will be cleared after the module is reset (reset to
factory settings).
5. TX and RX in UART0 are used for communication with external MCU powered by 3V.
Please refer to the description in 3.3. DC Characteristics for UART output current level.
6. It is recommended to ground unused GPIOs with 10pF capacitor.
7. GPIOA0 and GPIOA19 are Power on Trap Pin with functions described below:
PIN
Description
GPIO17
0：XO input is 26M (default)
1: XO input is 40M
GPIO14
0: 32k source is from external
1: 32k source is from internal (default)
GPIO16
0: boot up bypass boot ROM
1: boot up with boot ROM (default)
GPIO15
0: JTAG pin fixed for JTAG
1: JTAG pin as GPIO (default)
GPIO4
0: Boot with host interface disabled (default)
1: Boot with host interface enabled
Active if GPIO4=1
GPIO13
0: Host interface via SPI slave
1: Host interface via SDIO slave (default)
GPIO12
0: enter UART download mode
1: skip UART download (default)
The module will detect GPIO0 and GPIO19 when powered on and enter specific mode
according to the IO state.