Service manual

HL-5030/5040/5050/5070N SERVICE MANUAL
3-3
1.3 Main PCB
For the entire circuit diagram of the main PCB, see APPENDIX 1. to 7. ‘MAIN PCB CIRCUIT
DIAGRAM’ in this manual.
1.3.1 CPU
A Fujitsu 32bit RISC CPU, SPARClite is built in the ASIC. While the CPU is driven with a
clock frequency of 66.66 MHz in the user logic block, it itself runs at 133.33 MHz, which is
generated by multiplying the source clock by two.
<HL-5030/5040/5050>
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
ADR[1]
ADR[5]
ADR[6]
ADR[8]
ADR[9]
ADR[10]
ADR[2]
ADR[3]
ADR[4]
ADR[7]
ADR[11]
ADR[12]
ADR[13]
ADR[14]
ADR[22]
ADR[20]
ADR[15]
ADR[19]
ADR[17]
ADR[23]
ADR[21]
ADR[16]
ADR[18]
R94
33
R93
33
R92
33
R56
33
R49
33
R51
33
R63
51
R57
51
R42
51
6D/8D
ROMCSN0
6D
IOWEN
6D/8D
IORDN
8B
SDCLK0
8B
SDCKE0
8A
SDCSN0
6F/7C/7F/3-2E/
3-4D/3-4C/8A/
8B/3-2D
ADR[23-1]
7F/8F/3-6A
DATA[15-0]
RA12
22
2
7
1
8
3
6
4
5
RA15
22
2
7
1
8
3
6
4
5
RA13
22
2
7
1
8
3
6
4
5
RA14
22
2
7
1
8
3
6
4
5
RA9 10
2
7
1
8
3
6
4
5
RA8 10
2
7
1
8
3
6
4
5
RA11
10
2
7
1
8
3
6
4
5
RA10
10
2
7
1
8
3
6
4
5
VDD3
X2
AT-49 66.6666MHz
1
2
0V
C52
C100
C57
C2
R71
1M
R70
0
TP351
C43
C101
0V
R11
10k
R15
10k
R12
10k
R10
10k
R33
10k
VDD3
R38
10k
R34
10k
R35
10k
R36
10k
R37
10k
0V
R17
10k
R18
10k
R16
10k
R45
10k
R44
10k
0V
R65
0
R68
0
3-4C
SDCLK1
3-4C
SDCLK2
3-4C
SDCKE1
R61
0
3-2D
SDCSN1
3-2D
SDCSN2
R41
33
R50
33
R52
33
R48
33
3-2C
SDSDA
3-2C
SDSCL
R53
4.7k
VDD3
TP6
TP7
TP8
TP9
TP5
TP10
TP12
TP13
TP14
TP15
TP16
TP17
TP26
TP29
TP30
TP31
TP32
TP33
TP196
TP197
TP35
TP36
TP37
TP198
R19
10k
R39
10k
R47
10k
R46
10k
TP700
TP702
TP703
TP705
R62
4.7k
R58
4.7k
0V
TP726
TP727
TP728
TP729
TP730
TP731
TP732
TP733
TP734
U5
Aurora
DATA00
40
DATA01
41
DATA02
42
DATA03
43
DATA04
44
DATA05
45
DATA06
46
DATA07
47
DATA08
48
DATA09
49
DATA10
53
DATA11
54
DATA12
55
DATA13
56
DATA14
57
DATA15
58
DATA16/IO
59
DATA17/IO
60
DATA18/IO
61
DATA19/IO
62
DATA20/IO
63
DATA21/IO
64
DATA22/IO
67
DATA23/IO
68
DATA24/IO
69
DATA25/IO
70
DATA26/IO
71
DATA27/IO
72
DATA28/IO
73
DATA29/IO
74
DATA30/IO
75
DATA31/IO
76
EXINTN0
196
RSTN
216
SCKOUT
87
SCKIN
85
ADR01/24
9
ADR02
10
ADR03
11
ADR04
12
ADR05
13
ADR06
14
ADR07
15
ADR08
16
ADR09
17
ADR10
18
ADR11
19
ADR12
25
ADR13
26
ADR14
27
ADR15/BA0
28
ADR16/BA1
29
ADR17/RASN
30
ADR18/CASN
31
ADR19/WEN
32
ADR20/DQM0
33
ADR21/DQM1
34
ADR22/DQM2
35
ADR23/DQM3
36
ROMCSN0
211
ROMCSN1
212
IOWEN
213
IORDN
214
SDCLK0
95
SDCLK1
94
SDCLK2
93
SDCKE0
96
SDCKE1
97
SDCSN0
90
SDCSN1
89
SDCSN2
88
SDSDA
92
SDSCL
91
TP736
R90
33
R97
10
R98
10
R91
22
TP1000
TP1001
TP1002
TP1003
L6
0.82uH
C60
C103
0V
TP1009
Fig. 3-3