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March 2008 Rev 6 1/84

STM32F103x6

STM32F103x8 STM32F103xB

Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,

seven 16-bit timers, two ADCs and nine communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

■ Memories

– 32 to 128 Kbytes of Flash memory

– 6 to 20 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

■ 2 x 12-bit, 1 µs A/D converters (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Dual-sample and hold capability

– Temperature sensor

■ DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

Cs and USARTs

■ Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16

external interrupt vectors, all 5 V-tolerant

except for analog inputs

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

■ Up to 7 timers

– Up to three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 16-bit, 6-channel advanced control timer:

up to 6 channels for PWM output, dead-

time generation and emergency stop

– 2 watchdog timers (Independent and

Window)

– SysTick timer: a 24-bit downcounter

■ Up to 9 communication interfaces

– Up to 2 x I

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 2 SPIs (18 Mbit/s)

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

■ Packages are ECOPACK® (RoHS compliant)

Table 1. Device summary

Reference Root part number

STM32F103x6

STM32F103C6, STM32F103R6,

STM32F103T6

STM32F103x8

STM32F103C8, STM32F103R8

STM32F103V8, STM32F103T8

STM32F103xB

STM32F103RB STM32F103VB,

STM32F103CB

LQFP64

10 x 10 mm

LQFP100

14 x 14 mm

LQFP48

7 x 7 mm

BGA100

10 x 10 mm

VFQFPN36

6 × 6 mm

www.st.com

Summary of content (84 pages)

PAGE 1
STM32F103x6 STM32F103x8 STM32F103xB Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces Features ■ ■ ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division Memories – 32 to 128 Kbytes of Flash memory – 6 to 20 Kbytes of SRAM Clock, reset and supply management – 2.0 to 3.
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Contents STM32F103xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F103xx 6 7 5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.18 Temperature sensor characteristics . . . . . . . . . . . .
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List of tables STM32F103xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 4/84 Device summary . . . . . . . .
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STM32F103xx Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. List of tables RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STM32F103xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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STM32F103xx 1 Introduction Introduction This datasheet provides the STM32F103xx performance line ordering information and mechanical device characteristics. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming reference manual, PM0042, available from www.st.com. For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference Manual.
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Description 2.1 STM32F103xx Device overview Table 2.
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STM32F103xx 2.2 Description Overview ARM® CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Description STM32F103xx Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is monitored for failure. During such a scenario, it is disabled and software interrupt management follows. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).
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STM32F103xx Description Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in the nominal regulation mode (Run) ● LPR is used in the Stop mode ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered-down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset.
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Description STM32F103xx RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit registers) can be used to store data when VDD power is not present.
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STM32F103xx Description Advanced control timer (TIM1) The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for ● Input Capture ● Output Compare ● PWM generation (edge or center-aligned modes) ● One Pulse Mode output ● Complementary PWM outputs with programmable inserted dead-times.
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Description STM32F103xx Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB Full-speed 12 Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL.
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STM32F103xx Description STM32F103xx performance line block diagram TPIU SW/JTAG Ibus Cortex-M3 CPU Fmax : 72 MHz NVIC Trace Controlle r pbu s Trace/trig Dbus Syst em AHB:F max =48/72 MHz @VDDA SUPPLY SUPERVISION NRST VDDA VSSA Rst PVD Int PCLK1 PCLK2 HCLK FCLK AHB2 APB2 @VDD PLL & CLOCK MANAGT XTAL OSC 4-16 MHz GPIOA GPIOB PC[15:0] GPIOC PD[15:0] GPIOD PE[15:0] GPIOE 4 Chann els 3 co mpl.
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Description STM32F103xx Figure 2. Clock tree 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz 72 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..
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STM32F103xx Pin descriptions 3 Pin descriptions Figure 3.
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Pin descriptions STM32F103xx performance line LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4.
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STM32F103xx STM32F103xx performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 5.
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Pin descriptions PB7 PB6 PB5 PB4 PB3 PA15 PA14 36 BOOT0 STM32F103xx VFQFPN36 pinout VSS_3 35 34 33 32 31 30 29 28 VDD_3 1 27 VDD_2 OSC_IN/PD0 2 26 VSS_2 OSC_OUT/PD1 3 25 PA13 NRST 4 24 PA12 23 PA11 VSSA 5 VDDA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 PA8 PA2 9 10 11 12 13 14 15 PA3 PA4 PA5 PA6 PA7 PB0 QFN36 19 18 VDD_1 VSS_1 17 PB2 16 PB1 Figure 7.
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STM32F103xx Pin definitions Alternate functions LQFP64 LQFP100 VFQFPN36 Default LQFP48 Main function(3) (after reset) BGA100 Type(1) Pins I / O Level(2) Table 3.
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Pin descriptions Pin definitions (continued) Alternate functions LQFP48 LQFP64 LQFP100 VFQFPN36 Main function(3) (after reset) BGA100 Type(1) Pins I / O Level(2) Table 3.
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STM32F103xx Pin definitions (continued) LQFP48 LQFP64 LQFP100 VFQFPN36 F7 24 32 50 19 K8 J8 25 26 33 34 51 52 - - Pin name VDD_1 PB12 PB13 Type(1) BGA100 Pins I / O Level(2) Table 3.
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Pin descriptions Pin definitions (continued) Pin name Type(1) VFQFPN36 LQFP100 LQFP64 LQFP48 BGA100 Pins I / O Level(2) Table 3.
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STM32F103xx Pin definitions (continued) Alternate functions VFQFPN36 I2C1_SDA / CANTX LQFP100 Remap LQFP64 Default LQFP48 Main function(3) (after reset) BGA100 Type(1) Pins I / O Level(2) Table 3. Pin descriptions A4 46 62 96 - PB9 I/O FT PB9 TIM4_CH4(6) (7) D4 - - 97 - PE0 I/O FT PE0 TIM4_ETR(6) C4 - - 98 - PE1 I/O FT PE1 E5 47 63 99 36 VSS_3 S VSS_3 F5 48 64 100 1 VDD_3 S VDD_3 Pin name 1. I = input, O = output, S = supply, HiZ = high impedance.
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Memory mapping 4 STM32F103xx Memory mapping The memory map is shown in Figure 8. Figure 8.
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STM32F103xx 5 Electrical characteristics 5.1 Test conditions Electrical characteristics Unless otherwise specified, all voltages are referred to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25 °C and TA=TAmax (given by the selected temperature range).
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Electrical characteristics Figure 9. STM32F103xx Pin loading conditions Figure 10. Pin input voltage STM32F103xx pin STM32F103xx pin C = 50 pF VIN ai14141 5.1.6 ai14142 Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.
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STM32F103xx 5.1.7 Electrical characteristics Current consumption measurement Figure 12.
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Electrical characteristics 5.2 STM32F103xx Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics, Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4.
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STM32F103xx Electrical characteristics Table 6. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Operating conditions 5.3.1 General operating conditions Symbol Unit –65 to +150 °C 150 °C Maximum junction temperature 5.3 Table 7.
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Electrical characteristics 5.3.3 STM32F103xx Embedded reset and power control block characteristics The parameters given in Table 9 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 9.
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STM32F103xx 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 10 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 10. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ Max Unit −40 °C < TA < +105 °C 1.16 1.20 1.26 V −40 °C < TA < +85 °C 1.16 1.20 1.24 V 5.1 17.
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Electrical characteristics Table 11. STM32F103xx Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions Unit TA = 85 °C TA = 105 °C 72 MHz 50 50.3 48 MHz 36.1 36.2 36 MHz 28.6 28.7 24 MHz 19.9 20.1 16 MHz 14.7 14.9 8 MHz 8.6 8.9 72 MHz 32.8 32.9 48 MHz 24.4 24.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 19.8 19.9 13.9 14.2 16 MHz 10.7 11 8 MHz 6.8 7.
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STM32F103xx Electrical characteristics Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 45 40 Consumption (mA) 35 30 72MHz 36MHz 16MHz 8MHz 25 20 15 10 5 0 -40 0 25 70 85 105 Temperature (°C) Figure 14. Typical current consumption in Run mode versus frequency (at 3.
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Electrical characteristics Table 13. STM32F103xx Maximum current consumption in Sleep mode, code running from Flash or RAM Max Symbol Parameter Conditions fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz(2) 30 32 (3) 20 20.5 36 MHz(3) 15.5 16 MHz(3) 11.5 12 8.5 9 5.5 6 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.5 5 16 MHz 4 4.
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STM32F103xx Electrical characteristics Figure 15. Current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V Stop regulator ON 300 Consumption (µA) 250 200 3.3 V 150 3.6 V 100 50 0 -45 25 70 90 110 Temperature (°C) Figure 16. Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 300 Consumption (µA) 250 200 3.3 V 150 3.
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Electrical characteristics STM32F103xx Figure 17. Current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V Standby mode 3.5 Consumption (µA) 3 2.5 2 3.3 V 1.5 3.6 V 1 0.5 0 -45 25 70 90 110 Temperature (°C) Typical current consumption The MCU is placed under the following conditions: 38/84 ● All I/O pins are in input mode with a static value at VDD or VSS (no load). ● All peripherals are disabled except if it is explicitly mentioned.
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STM32F103xx Table 15. Electrical characteristics Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 36 27 48 MHz 24.2 18.6 36 MHz 19 14.8 24 MHz 12.9 10.1 16 MHz 9.3 7.4 8 MHz 5.5 4.6 4 MHz 3.3 2.8 2 MHz 2.
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Electrical characteristics Table 16. STM32F103xx Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM Typ(1) Symbol Parameter Conditions External clock IDD Supply current in Sleep mode (3) fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 14.4 5.5 48 MHz 9.9 3.9 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1 1 MHz 1.11 0.98 500 kHz 1.04 0.96 125 kHz 0.98 0.
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STM32F103xx Electrical characteristics Table 17. Symbol IDD IDD_VBAT Typical current consumption in Standby mode VDD Typ(1) Low-speed internal RC oscillator and independent watchdog OFF 3.3 V 2 2.4 V 1.5 Supply current in Low-speed internal RC oscillator and Standby mode(2) independent watchdog ON 3.3 V 3.4 2.4 V 2.6 Low-speed internal RC oscillator ON, independent watchdog OFF 3.3 V 3.2 2.4 V 2.4 3.3 V 1.4 2.4 V 1.
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Electrical characteristics Table 18. STM32F103xx Peripheral current consumption(1) Peripheral Typical consumption at 25 °C TIM2 1.2 TIM3 1.2 TIM4 0.9 SPI2 0.2 USART2 0.35 USART3 0.35 I2C1 0.39 I2C2 0.39 USB 0.65 CAN 0.715 GPIO A 0.47 GPIO B 0.47 GPIO C 0.47 GPIO D 0.47 GPIO E 0.47 ADC1(2) 1.81 ADC2 1.78 TIM1 1.6 SPI1 0.43 USART1 0.85 Unit APB1 mA APB2 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2.
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STM32F103xx Electrical characteristics Table 19. High-speed external (HSE) user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE_ext User external clock source frequency(1) 8 25 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 16 tr(HSE) tf(HSE) OSC_IN rise or fall time(1) V IL ns OSC_IN Input leakage current 5 VSS ≤VIN ≤VDD ±1 µA 1.
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Electrical characteristics STM32F103xx Low-speed external user clock The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 7. Table 20.
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STM32F103xx Electrical characteristics Figure 19.
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Electrical characteristics STM32F103xx High-speed external clock The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21.
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STM32F103xx Electrical characteristics Low-speed external clock The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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Electrical characteristics 5.3.7 STM32F103xx Internal clock source characteristics The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. High-speed internal (HSI) RC oscillator Table 23.
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STM32F103xx Electrical characteristics Wakeup time from low-power mode The wakeup times given in Table 25 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● Stop or Standby mode: the clock source is the RC oscillator ● Sleep mode: the clock source is the clock that was set before entering Sleep mode.
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Electrical characteristics 5.3.9 STM32F103xx Memory characteristics Flash memory The characteristics are given at TA = −40 to 105 °C unless otherwise specified. Table 27. Symbol tprog tERASE tME IDD Vprog Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = −40 to +105 °C 40 52.5 70 µs Page (1kB) erase time TA = −40 to +105 °C 20 40 ms Mass erase time TA = −40 to +105 °C 20 40 ms Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.
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STM32F103xx 5.3.10 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32F103xx Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J 1752/3 standard which specifies the test board and the pin loading. Table 30. Symbol EMI characteristics Parameter SEMI 5.3.11 Peak level Conditions Monitored Frequency Band 0.1 to 30 MHz VDD = 3.
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STM32F103xx 5.3.12 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under the conditions summarized in Table 7. All I/Os are CMOS and TTL compliant. Table 33. Symbol VIL I/O static characteristics Parameter Conditions Input low level voltage (1) Standard IO input high level voltage(1) VIH VIL VIH Ilkg 2 VDD+0.5 2 5.5V –0.5 0.35 VDD 0.65 VDD VDD+0.
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Electrical characteristics STM32F103xx Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 5).
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STM32F103xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 35, respectively. Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 35.
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Electrical characteristics STM32F103xx Figure 22. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 33).
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STM32F103xx Electrical characteristics Figure 23. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset FILTER 0.1 µF STM32F10xxx ai14132b 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 36. Otherwise the reset will not be taken into account by the device. 5.3.
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Electrical characteristics 5.3.15 STM32F103xx Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 7. The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain.
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STM32F103xx Electrical characteristics Figure 24. I2C bus AC waveforms and measurement circuit VDD VDD 4 .7 kΩ 4 .7 kΩ 100Ω STM32F103xx SDA I2C bus 100Ω SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) tw(SCKL) th(STA) SCL tw(SCKH) tsu(SDA) tr(SCK) th(SDA) tsu(STA:STO) S TOP tsu(STO) tf(SCK) ai14149b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 39. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)(3) I2C_CCR value fSCL (kHz) RP = 4.
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Electrical characteristics STM32F103xx SPI interface characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 7. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40.
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STM32F103xx Electrical characteristics Figure 25. SPI timing diagram - slave mode and CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN LSB IN B I T1 IN th(SI) ai14134 Figure 26.
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Electrical characteristics STM32F103xx Figure 27. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INP UT tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 41.
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STM32F103xx Electrical characteristics Figure 28. USB timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S Table 43. tf tr ai14137 USB: Full speed electrical characteristics Symbol Parameter Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Driver characteristics tr tf trfm VCRS Rise time(1) Fall time(1) Rise/ fall time matching Output signal crossover voltage 1.
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Electrical characteristics 5.3.17 STM32F103xx 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 7. Note: It is recommended to perform a calibration after each power-up. Table 44. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA ADC power supply 2.4 3.6 V VREF+ Positive reference voltage 2.
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STM32F103xx Electrical characteristics Equation 1: RAIN max formula: t S R AIN < --------------------------------------------------------------- – R ADC N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 45. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 1.2 7.5 0.54 10 13.5 0.96 19 28.5 2.04 41 41.5 2.96 60 55.
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Electrical characteristics STM32F103xx Table 47. ADC accuracy(1) (2) Symbol Parameter ET EO Test conditions Total unadjusted error(4) Offset error(3) (3) EG Gain error ED Differential linearity error(3) EL Integral linearity error (3) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(3) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
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STM32F103xx Electrical characteristics Figure 30. Typical connection diagram using the ADC VDD RAIN(1) VAIN STM32F103xx VT 0.6 V AINx VT 0.6 V CAIN RADC(1) 12-bit A/D conversion CADC(1) IL±1 µA ai14150b 1. Refer to Table 44 for the values of CAIN, RAIN, RADC and CADC. 2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy.
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Electrical characteristics STM32F103xx Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages. 5.3.18 Temperature sensor characteristics Table 48. TS characteristics Symbol Parameter TL(1) VSENSE linearity with temperature Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Conditions Min Max Unit ±1 ±2 °C Average slope 4.0 4.
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STM32F103xx 6 Package characteristics 6.1 Package mechanical data Package characteristics In order to meet environmental requirements, ST offers the STM32F103xx in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
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Package characteristics STM32F103xx Figure 33. VFQFPN36 6 x 6 mm, 0.5 mm pitch, Figure 34. Recommended footprint package outline(1) (dimensions in mm)(1)(2)(3) Seating plane C ddd C 4.30 A2 A 36 A1 A3 D 27 4.80 36 28 27 E2 1 Pin # 1 ID R = 0.20 e 1 4.80 6.30 b 4.10 4.30 4.10 E 0.30 18 19 0.75 9 19 9 10 18 1.00 0.50 10 4.30 D2 L ai14870 ZR_ME 1. Drawing is not to scale. 2. The back-side pad is not internally connected to the VSS or VDD power pads. 3.
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STM32F103xx Package characteristics Figure 35. LFBGA100 - low profile fine pitch ball grid array package outline C Seating plane ddd C A2 A4 A3 A1 A D B D1 F e A K J H G F E D C B A F E1 E e 1 2 3 4 5 6 7 8 9 10 A1 corner index area (see note 5) ∅b (100 balls) ∅eee M C A B ∅ fff M C Bottom view ai14396 1. Drawing is not to scale. Table 50. LFBGA100 - low profile fine pitch ball grid array package mechanical data inches(1) mm Dim. Min Typ A A1 Max Min Typ 1.700 Max 0.
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Package characteristics STM32F103xx Figure 36. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.
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STM32F103xx Package characteristics Figure 38. Recommended footprint(1)(2) Figure 37. LQFP100, 100-pin low-profile quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE 75 k 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 25 26 Pin 1 1 identification 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 51.
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Package characteristics STM32F103xx Figure 40. Recommended footprint(1)(2) Figure 39. LQFP64, 64-pin low-profile quad flat package outline(1) D A D1 A2 48 33 0.3 A1 49 b E1 12.7 32 0.5 10.3 E e 10.3 64 17 1.2 1 16 c 7.8 L1 12.7 L ai14398 ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 52. LQFP64, 64-pin low-profile quad flat package mechanical data inches(1) mm Dim. Min Typ A Max Min 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.
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STM32F103xx Package characteristics Figure 41. LQFP48, 48-pin low-profile quad flat package outline(1) Figure 42. Recommended footprint(1)(2) D A D1 A2 0.50 1.20 A1 13 0.30 24 25 12 b 9.70 E1 0.20 7.30 5.80 e E 7.30 1 36 48 37 1.20 c L1 5.80 L 9.70 ai14911 ai14399 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 53. LQFP48, 48-pin low-profile quad flat package mechanical data inches(1) mm Dim. Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.
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Package characteristics 6.2 STM32F103xx Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 7: General operating conditions on page 31.
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STM32F103xx 6.2.2 Package characteristics Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 55: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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Package characteristics STM32F103xx Using the values obtained in Table 54 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 55: Ordering information scheme). Figure 43. LQFP100 PD max vs.
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STM32F103xx 7 Ordering information scheme Ordering information scheme Table 55.
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Revision history 8 STM32F103xx Revision history Table 56. Document revision history Date Revision 01-jun-2007 1 Initial release. 2 Flash memory size modified in Note 6, Note 4, Note 7, Note 8 and BGA100 pins added to Table 3: Pin definitions. Figure 3: STM32F103xx performance line BGA100 ballout added. THSE changed to TLSE in Figure 19: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes.
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STM32F103xx Revision history Table 56. Document revision history (continued) Date 18-Oct-2007 Revision Changes 3 STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: Device features and peripheral counts (STM32F103xx performance line)) VFQFPN36 package added (see Section 6: Package characteristics). All packages are ECOPACK® compliant. Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see Section 6: Package characteristics).
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Revision history STM32F103xx Table 56. Document revision history (continued) Date 22-Nov-2007 82/84 Revision Changes 4 Document status promoted from preliminary data to datasheet. The STM32F103xx is USB certified. Small text changes. Power supply schemes on page 10 modified. Number of communication peripherals corrected for STM32F103Tx and number of GPIOs corrected for LQFP package in Table 2: Device features and peripheral counts (STM32F103xx performance line).
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STM32F103xx Revision history Table 56. Document revision history (continued) Date 14-Mar-2008 21-Mar-2008 Revision Changes 5 Figure 2: Clock tree on page 16 added. Maximum TJ value given in Table 6: Thermal characteristics on page 31. CRC feature added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 8: Memory map on page 26 for address). IDD modified in Table 14: Typical and maximum current consumptions in Stop and Standby modes.
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STM32F103xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.