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VS-GA100TS120UPbF www.vishay.
VS-GA100TS120UPbF www.vishay.com Vishay Semiconductors ELECTRICAL SPECIFICATIONS (TJ = 25 °C unless otherwise specified) PARAMETER Collector to emitter breakdown voltage Collector to emitter voltage Gate threshold voltage Temperature coefficient of threshold voltage SYMBOL V(BR)CES VCE(on) VGE(th) VGE(th)/TJ Forward transconductance gfe Collector to emitter leaking current ICES Maximum diode forward voltage VFM Gate to emitter leakage current IGES TEST CONDITIONS MIN. TYP. MAX.
VS-GA100TS120UPbF www.vishay.com Vishay Semiconductors THERMAL AND MECHANICAL SPECIFICATIONS PARAMETER SYMBOL Thermal resistance, junction to case IGBT TEST CONDITIONS RthJC Diode Thermal resistance, case to sink per module RthCS case to heatsink Mounting torque case to terminal 1, 2 and 3 For screws M5 x 0.8 Weight of module TYP. MAX. - 0.24 - 0.35 0.1 - - 4.0 - 3.
VS-GA100TS120UPbF www.vishay.com VCE - Collector to Emitter Voltage (V) Vishay Semiconductors TC - Case Temperature (°C) 160 140 120 DC 100 80 60 40 20 0 0 40 80 120 160 3.0 VGE = 15 V 500 µs pulse width IC = 200 A 2.5 IC = 100 A 2.0 IC = 50 A 1.5 0 200 30 60 90 120 150 Maximum DC Collector Current (A) TJ - Junction Temperature (°C) Fig. 4 - Case Temperature vs. Maximum Collector Current Fig. 5 - Typical Collector to Emitter Voltage vs.
VS-GA100TS120UPbF www.vishay.com Vishay Semiconductors 300 IC - Collector Current (A) Total Switching Losses (mJ) 40 35 30 25 200 100 Safe operating area 20 0 10 20 30 40 50 0 300 900 1200 Fig. 9 - Typical Switching Losses vs. Gate Resistance Fig. 12 - Reverse Bias SOA IC = 200 A IC = 100 A 10 IC = 50 A 0 30 60 90 120 150 IF - Instantaneous Forward Current (A) VCE - Collector to Emitter Voltage (V) 1 1500 1000 100 TJ = 125 °C TJ = 25 °C 10 1 0.5 1.0 1.5 2.0 2.5 3.
VS-GA100TS120UPbF www.vishay.com Vishay Semiconductors 240 250 VR = 720 V TJ = 125 °C TJ = 25 °C IF = 200 A IF = 100 A IF = 50 A 200 IF = 200 A IF = 100 A IF = 50 A 160 IRRM (A) trr (ns) 200 150 100 120 VR = 720 V TJ = 125 °C TJ = 25 °C 50 80 400 800 1600 1200 2000 0 400 800 dIF/dt (A/µs) Fig. 16 - Typical Recovery Current vs. dIF/dt L2 Gate voltage D.U.T. + 10 % + VG L RG2 + V - CC 2000 dIF/dt (A/µs) Fig. 15 - Typical Reverse Recovery Time vs.
VS-GA100TS120UPbF www.vishay.com Vishay Semiconductors VG Gate signal device under test Current D.U.T. Voltage in D.U.T. Current in D1 t0 t1 t2 Fig. 17e - Macro Waveforms for Figure 18a‘s Test Circuit L 1000 V D.U.T. VC* 50 V RL = 0 - 480 V 6000 µF 100 V 480 V 4 x IC at 25 °C * Driver same type as D.U.T.; VC = 80 % of VCE (max) Note: Due to the 50 V power supply, pulse width and inductor will increase to obtain rated Id Fig. 18 - Clamped Inductive Load Test Circuit Fig.
VS-GA100TS120UPbF www.vishay.com Vishay Semiconductors CIRCUIT CONFIGURATION 3 6 7 1 4 5 2 LINKS TO RELATED DOCUMENTS Dimensions Revision: 26-Mar-12 www.vishay.com/doc?95173 Document Number: 94428 8 For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.
Outline Dimensions www.vishay.com Vishay Semiconductors INT-A-PAK IGBT Ø 6.5 (Ø 0.25) 80 (3.15) 23 (0.91) 14.3 (0.56) 23 (0.91) 5 (0.20) 2.8 x 0.8 (0.11 x 0.03) 14.5 (0.57) 2 3 5 1 66 (2.60) 3 screws M6 x 10 4 35 (1.38) 7 6 17 (0.67) 29 (1.15) 28 (1.10) 9 (0.33) 30 (1.18) 7 (0.28) DIMENSIONS in millimeters (inches) 37 (1.44) 94 (3.70) Revision: 27-Mar-13 Document Number: 95173 1 For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.
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