Specifications

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TNETX4090

ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET



SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Single-Chip 100-/1000-Mbit/s Device

Integrated Physical Coding Sublayer (PCS)

Logic Provides Direct Interface to Gigabit

Transceivers

Integrated Address-Lookup Engine and

Table Memory for 2-K Addresses

Supports IEEE Std 802.1Q Virtual-LAN

(VLAN) Tagging Scheme

Provides Data Path for Network

Management Information [No External

Media-Access Control (MAC) Required]

Full-Duplex IEEE Std 802.3 Flow Control

Half-Duplex Back-Pressure Flow Control

Fully Nonblocking Architecture Using

High-Bandwidth Rambus Memory

Simple Expansion Via the Gigabit Interface

for Higher-Density Port Solutions

Port Trunking/Load Sharing for

High-Bandwidth Interswitch Links

Supports Pretag Extended Port Awareness

EEPROM Interface for Autoconfiguration

(No CPU Required for Nonmanaged Switch)

Provides Direct Input/Output (DIO) Interface

for Configuration and Statistics Information

Supports On-Chip Per-Port Storage for

Etherstat and Remote Monitoring (RMON)

Management Information Bases (MIBs)

Fabricated in 2.5-/3.3-V Low-Voltage

Technology

Supports Ring-Cascade Mode

Supports Spanning Tree

Packaged in 352-Terminal Ball Grid Array

Package

description

The TNETX4090 is a 9-port 100-/1000-Mbit/s nonblocking Ethernet switch with an on-chip address-lookup

engine. The TNETX4090 provides a low-cost, high-performance switch solution. The TNETX4090 is a fully

manageable desktop switch solution achieved by combining the TNETX4090 with physical interfaces and

high-bandwidth rambus-based packet memory and a CPU. The TNETX4090 also provides an interface capable

of receiving and transmitting simple-network management protocol (SNMP) and bridge protocol data units

(BPDU) (spanning tree) frames.

The TNETX4090 provides eight 10-/100-Mbit/s interfaces and one 100-/1000-Mbit/s interface. In half-duplex

mode, all ports support back-pressure flow control to reduce the risk of data loss for a long burst of activity. In

the full-duplex mode of operation, the device uses IEEE Std 802.3 frame-based flow control. With full-duplex

capability, ports 0–7 support 200-Mbit/s aggregate bandwidth connections. Port 8 supports 2 Gbit/s to desktops,

high-speed servers, hubs, or other switches in the full-duplex mode. The physical coding sublayer (PCS)

function is integrated on chip to provide a direct 10-bit interface to the gigabit Ethernet transceiver. The

TNETX4090 also supports port trunking/load sharing on the 10-/100-Mbit ports. This can be used to group ports

on interswitch links to increase the effective bandwidth between the systems. In the ring-cascade mode, port 8

can be used to connect multiple devices in a ring topology, which provides a low-cost, high-port-density desktop

switch. Pretagging and extended port awareness allow the TNETX4090 to be used as a front end to a router

or crossbar switch to build a cost-effective, high-density, high-performance system.

The internal address-lookup engine (IALE) supports up to 2-K unicast/multicast and broadcast addresses and

up to 64 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or

non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support

VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown

source- and destination-address packets to ports specified via programmable masks.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI, ThunderSWITCH, and ThunderSWITCH II are trademarks of Texas Instruments Incorporated.

Ethernet and Etherstat are trademarks of Xerox Corporation.

Secure Fast Switching is a trademark of Cabletron Systems, Inc.

Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast

Switching.

Summary of content (78 pages)

PAGE 1
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 D D D D D D D D D Single-Chip 100-/1000-Mbit/s Device Integrated Physical Coding Sublayer (PCS) Logic Provides Direct Interface to Gigabit Transceivers Integrated Address-Lookup Engine and Table Memory for 2-K Addresses Supports IEEE Std 802.
PAGE 2
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 description (continued) MII MII MII MII MII MII MII MII 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC EEPROM I/F CPU I/F With DMA Local Packet Switching Memory MDIO I/F Switching Engine (Queue Manager) Rambus DRAM Controller 100-M Management MAC VLAN 802.
PAGE 3
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DIO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Receiving/Transmitting Management Frames . . . . . . . . . . .
PAGE 4
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 GGP PACKAGE (BOTTOM VIEW) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAGE 5
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 1.
PAGE 6
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) (Continued) SIGNAL NAME RESET SAD0 SAD1 SCS SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 6 BALL NO. M23 AF22 AE22 AD22 AF20 AE20 AD20 AC20 AF21 AE21 AD21 AC21 SIGNAL NAME SDMA SINT SRDY SRNW SRXRDY STXRDY TCLK TDI TDO TMS TRST VDD(2.5) BALL NO.
PAGE 7
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions JTAG interface TERMINAL I/O INTERNAL RESISTOR† DESCRIPTION L24 I Pullup Test clock. Clocks state information and test data into and out of the TNETX4090 during operation of the test port. TDI M24 I Pullup Test data input. Serially shifts test data and test instructions into the TNETX4090 during operation of the test port.
PAGE 8
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface (GMII mode) TERMINAL NAME I/O INTERNAL RESISTOR† DESCRIPTION I Pulldown Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision. Additionally, during full-duplex operation, transmission of new frames does not commence if this terminal is asserted. M08_CRS I Pulldown Carrier sense.
PAGE 9
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface [physical media attachment (PMA) mode] TERMINAL NAME I/O INTERNAL RESISTOR DESCRIPTION M08_COL I Pulldown Receive byte clock 1. M08_COL is used to input receive byte clock 1 from the attached SERDES device. M08_CRS I Pulldown Unused. This terminal can be left unconnected. M08_EWRAP O None Enable wrap.
PAGE 10
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] TERMINAL NAME I/O INTERNAL RESISTOR DESCRIPTION I Pulldown Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision. Additionally, during full-duplex operation, transmission of new frames does not commence if this terminal is asserted.
PAGE 11
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] (continued) TERMINAL NAME I/O INTERNAL RESISTOR DESCRIPTION M08_TXEN O None Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD3–M08_TXD0. This signal is synchronous to M08_RFCLK. M08_TXER O None Transmit error.
PAGE 12
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL RESISTOR DESCRIPTION C26 D26 D1 C1 F3 F2 AA3 O None Renegotiate. Indicates to the attached PHY device that this port wishes to renegotiate a new configuration.
PAGE 13
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL RESISTOR C19 C14 B9 B4 L4 T3 AA2 AD8 I Pulldown M00_TCLK M01_TCLK M02_TCLK M03_TCLK M04_TCLK M05_TCLK M06_TCLK M07_TCLK B23 C17 C13 A8 F1 L2 T1 AD4 I Pullup M00_TXD3 M00_TXD2 M00_TXD1 M00_TXD0 M01_TXD3 M01_TXD2 M01_TXD1 M01_TXD0 M02_TXD3 M02_TXD2 M02_TXD1 M02_TXD0 M03
PAGE 14
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL RESISTOR DESCRIPTION D22 B17 B13 B8 H4 L1 V3 AE4 O None Transmit enable. Indicates valid transmit data on Mxx_TXDn. This signal is synchronous to Mxx_TCLK. D21 A17 D11 C8 H3 N3 V2 AF4 O None Transmit error. Allows coding errors to be propagated across the MII.
PAGE 15
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) RDRAM interface TERMINAL I/O INTERNAL RESISTOR DESCRIPTION Y26 O None Bus control. Controls signal-to-frame packets, transmits part of the operation code, initiates data transfers, and terminates data transfers. This is a rambus signal logic (RSL) signal (see Note 1). AC26 AA24 AB26 Y24 V24 U25 U26 T26 R25 I/O None Bus data.
PAGE 16
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) DIO interface TERMINAL NAME NO. I/O INTERNAL RESISTOR DESCRIPTION SAD0 SAD1 AF22 AE22 I Pullup DIO address bus. Selects the internal host registers provided SDMA is high. Internal pullup resistors are provided. SCS AD22 I Pullup DIO chip select. When low, SCS indicates a DIO port access is valid. An internal pullup resistor is provided.
PAGE 17
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) LED interface TERMINAL I/O INTERNAL RESISTOR AD19 O None LED clock. Serial shift clock for the LED status data. AE19 O None LED data. Serial LED status data. NAME NO. LED_CLK LED_DATA DESCRIPTION 100-/1000-Mbit/s port PCS LED interface TERMINAL NAME L08_DPLX I/O NO. AE18 INTERNAL RESISTOR DESCRIPTION None Duplex LED.
PAGE 18
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface description The DIO is a general-purpose interface that is used with a range of microprocessor or computer system interfaces. The interface is backward compatible with the existing TI ThunderSWITCH products. The DIO provides new signals to support external DMA controllers for improved performance.
PAGE 19
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2.
PAGE 20
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2.
PAGE 21
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2.
PAGE 22
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2.
PAGE 23
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2.
PAGE 24
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface description (continued) Table 3 and Table 4 list the least significant byte address for the port-specific statistics. Each statistic is four bytes long. To determine the address of a particular statistic, replace the xx in the head column with the characters from the tail address. Table 3 has two tail columns: one for even-numbered ports and the other for odd-numbered ports.
PAGE 25
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 3. Port Statistics 1 TAIL PORT NO.
PAGE 26
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 4. Port Statistics 2 TAIL (ALL PORTS) PORT NO.
PAGE 27
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface description (continued) Table 5. Address-Lookup Statistics PORT NO.
PAGE 28
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 state of DIO signal terminals during hardware reset The CPU can perform a hardware reset by writing to an address in the range of 0x40–0x5F (writes to a DMA address in this range have no effect on reset); this is equivalent to asserting the hardware RESET terminal with the following exceptions. During hardware reset, the output and bidirectional DIO terminals behave as shown in Table 7.
PAGE 29
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 frame format on the NM port (continued) To provide a CRC word, which includes the header, the NM port generates a new CRC word as the frame is being read out. It simultaneously checks the existing CRC in the frame and, if an error is found, ensures that the final byte of the newly generated CRC is corrupted to contain an error, too.
PAGE 30
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 frame format on the NM port (continued) Any device reading frames out of the NM port must expect frames to be in the format shown in Figure 2.
PAGE 31
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 full-duplex NM port The NM port can intermix reception and transmission as desired. It is the direction of the NMData access (i.e., read or write) that determines whether a byte is removed from the transmit queue or added to the receive queue. The DIO interface, however, is only half duplex since it cannot do a read and write at the same time.
PAGE 32
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MAC interface receive control Data received from the PHYs is interpreted and assembled into the TNETX4090 buffer memory. Interpretation involves detection and removal of the preamble, extraction of the address and frame length, extraction of the IEEE Std 802.1Q header (if present), and data handling and CRC.
PAGE 33
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 adaptive performance optimization (APO) Each Ethernet MAC incorporates APO logic. This can be enabled on an individual port basis. When enabled, the MAC uses transmission pacing to enhance performance (when connected on networks using other transmit pacing-capable MACs).
PAGE 34
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 10-/100-Mbit/s MII (ports 0–7) speed, duplex, and flow-control negotiation Each individual port can operate at 10 Mbit/s or 100 Mbit/s in half or full duplex, and can indicate (or not) support of IEEE Std 802.3 flow control. The operating modes for each port can be negotiated between the MACs and the PHYs after power up, by setting neg in PortxControl.
PAGE 35
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 TXCLK TXEN TXER ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Reserved Reserved TXD3 Reserved Speed TXD2 TXD1 Reserved Pause Reserved Duplex TXD0 LINK RXCLK RXDV RXER ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ RXD3 RXD2 RXD1 RXD0 Reserved Reserved Reserved Speed Reserved Pause Reserved Duplex 80-ms Min 1200-ms Min Link Fail or Renegotiate Autonegotiate Page Swa
PAGE 36
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 100-/1000-Mbit/s PHY interface (port 8) This port is controlled by an IEEE Std 802.3-compliant MAC. speed, duplex, and flow-control negotiation When in PMA mode and autonegotiation is enabled, the on-chip PCS layer attempts to establish a compatible mode of operation with the attached serializer/deserializer (SERDES).
PAGE 37
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 speed, duplex, and flow-control negotiation (continued) In 100-Mbit/s mode, M08_RXD4 and M08_RXD5 are reconfigured as open-drain inputs, to allow the port to negotiate with the PHY device for duplex and IEEE Std 802.3 pause frame support at power up via the EEPROM contents. M08_RXD4 is used for duplex and M08_RXD5 is used for pause (see Table 8 and Table 9).
PAGE 38
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 pretagging and extended port awareness The TNETX4090 can be incorporated into a hierarchical system, whereby this port is connected to a crossbar matrix with up to 17 1000-Mbit/s ports. By making this TNETX4090 aware of the ports on the crossbar matrix, the crossbar matrix does not need to make any forwarding or filtering decisions, and can be relatively inexpensive.
PAGE 39
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 10. Transmit Pretag Bit Definitions BIT NAME FUNCTION 31–28 reserved Reserved. These bits always are 0. 27 rxheader 26–25 reserved Reserved. These bits always are 0. 24–20 portcode Source port code. Indicates which port on the device received the frame. Codes 00000–01001 indicate ports 0–9, respectively (port 9 is the NM DIO port).
PAGE 40
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 12. Directed Format Receive Pretag Bit Definitions BIT NAME FUNCTION One. Indicates directed format. The frame is routed to port(s) specified in portvector that are enabled (disabled in portxcontrol = 0), regardless of whether the destination address is unicast or multicast (i.e., the destination address is not examined).
PAGE 41
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 ring-cascade topology (continued) D Frames received on a ring port must have an out-of-band pretag in the clock cycle before Mxx_RXDV is asserted. The contents of the pretag are examined, and based on the results, are either forwarded normally, or immediately discarded within the MAC. If discarded, the frame does not affect any of the statistics or address-lookup database.
PAGE 42
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 EEPROM interface The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less preconfigured system. This also can be used to change or reconfigure the system and retain the preferences between system power downs. The EEPROM contains configuration and initialization information that is accessed infrequently, typically at power up and after a reset.
PAGE 43
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 EEPROM interface (continued) After the initial start condition, a slave address containing a device address of 000 is output on EDIO, and then EDIO is observed for an acknowledge from the EEPROM. If an acknowledge is received, operation continues for the 24C02 EEPROM.
PAGE 44
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 compatibility with future device revisions All EEPROM locations that correspond to reserved addresses in the memory map, register bits that are read only, and register bits that are marked as reserved should be set to 0 to ensure compatibility with future versions of the device. Failure to do so may result in the unintentional activation of features in future devices.
PAGE 45
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 17. LED Status Bit Definitions and Shift Order ORDER slast = 0 1st–12th slast = 1 11th–22nd NAME FUNCTION SW0–SW11 Software LEDs 0–11. These allow additional software-controlled status to be displayed. These 12 LEDs reflect the values of bits 0–11 of the swied field in LEDControl at the moment that the LED interface samples them.
PAGE 46
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH DBUS_CTL DBUS_EN DRX_CLK DTX_CLK BUS_CLK DBUS_DATA8–DBUS_DATA0 SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 TNETX4090 VCC 9 TXCLK RXCLK BUS ENABLE BUS CTRL BUS DATA (8–0) TXCLK RXCLK BUS ENABLE BUS CTRL BUS DATA (8–0) TXCLK RXCLK BUS ENABLE BUS CTRL BUS DATA (8–0) Concurrent RDRAM Concurrent RDRAM Concurrent RDRAM VREF VDD GND SIN SOUT VREF VDD GND SIN SOUT VREF VDD GND SIN SOUT Clock Source NC – No internal connection
PAGE 47
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 JTAG interface The TNETX4090 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAG terminals to eliminate the need for external ones.
PAGE 48
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 frame routing VLAN support The internal routing engine supports the IEEE Std 802.1Q VLANs as shown in Figure 11 and described in the following paragraphs. Receive IEEE Std 802.1Q Format Frame Header If rxacc = 1 Header Inserted If VLAN ID = 0x000 VLAN ID Replaced Record Number NonIEEE Std 802.
PAGE 49
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 IEEE Std 802.1Q tags – reception By the time the IALE examines the received frame, it contains an IEEE Std 802.1Q tag header (after the source address). The tag used depends on the port configuration. If the port is configured as an access port, IALE always uses the default VID programmed for this port and assumes that all received frames on this port are untagged.
PAGE 50
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 aging algorithms time-threshold aging When learning addresses, the IALE adds the address to the table and tags it with a time stamp. If another frame is received with this address, the time stamp is refreshed. If the aging counter expires before another frame is received from this source address, the address is deleted from the table.
PAGE 51
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Start Key: UnkVLAN No Known VLAN? interrupt statistic Yes Unkmem No Source Port = 1 in. VLANnPorts? Yes Yes Yes Destination Locked Bit = 1? No No Yes Destination Address Found? No Destination is Multicast? Destination is Multicast? Yes Source Port Blocked by RxUniBlockPorts and Dest. Nblck=0? Yes No Source Port Blocked by RxMultiBlockPorts and Dest.
PAGE 52
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 A B Source Address Found? No Source Port = 1 in NLearnPorts? new No Yes Yes Source Locked Bit = 1? No Source Port Moved? No Yes Yes Unknown Source secvio Source Secure Bit = 1? Yes Source Port Security Violation Discard Frame No No chng Stayed Within a Trunk? Yes Yes Source Port = 1 in RingPorts? Yes No Remove Source Port (and other trunk members) From Port Routing Co
PAGE 53
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 C E D Remove: – Disabled Ports – Ports Blocked by TxBlockPorts From Port Routing Code If Mirr Bit = 1? Yes [(Source Port = MirrorPort or Port Routing Code Includes MirrorPort) and (Source Port ! = UplinkPort)] Then Include UplinkPort in Port Routing Code No Lshare = 1? Yes Destination Found? No Yes Port Routing Code is Adjusted by Trunking Algorithm (see Note A) Port Routing Cod
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 removal of source port Normally, the IALE does not route a frame to a port on which it was received. The port routing code is examined to see if the source port is included. If so, the port routing code is modified to remove the source port. If the bit in RingPorts corresponding to the port that received the frame is set, the port routing code is not modified to remove the source port.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 port trunking example This example shows how to set up the TNETX4090 to support two port trunks. The first trunk group consists of ports 1, 3, 5, and 7 (see Table 21); the second trunk group consists of ports 0, 2, and 6 (see Table 22). Table 21. Trunk Group 0 Port Membership (Trunk0Ports Register) PORT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 Table 22.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 flow control The TNETX4090 supports collision-based flow control for ports in half-duplex mode and IEEE Std 802.3x flow control for ports in full-duplex mode. The flow bit in the SysControl register determines the action that will be taken when back pressure is needed, that is, when there are insufficient resources to handle an inbound packet.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 other flow-control mechanisms hardware flow control If a port were in MII or GMII mode and full duplex, normally, its Mxx_COL would not be needed. Hardware flow control has been added by preventing the start of a frame transmission if the Mxx_COL is high. This is useful in ring mode; the Mxx_COL can be tied to the FLOW of the upstream neighbor for hardware flow control.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 reading RDRAM Reading from RDRAM memory is accomplished as follows: 1. Write the byte address for the access to ramaddress in RAMAddress. 2. Set rdwrite = 1 and rdram = 1 (these can be written simultaneously). 3. Poll rdram until it becomes 0. This indicates that the read has completed. 4. Read the data for the access to RAMData.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 internal wrap test (continued) 08 07 06 NM TNETX4090 05 04 03 02 01 00 Figure 13. Internal Wrap Example The operational status of the PHYs or external connections to the device do not have to be considered or assumed good, when in internal loopback mode. duplex wrap test Duplex wrap test is similar to internal wrap mode (see Figure 13).
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD(2.5) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.7 V Supply voltage range, VDD(3.3) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOH VOL High-level output voltage IOZ TEST CONDITIONS Low-level output voltage IOH = rated IOL = rated High-impedance-state output current VO = VDD or GND IIH IIL High-level input current Low-level input current VI = VIH VI = VIL VOHR VOLR High-level output voltage (RSL) IOH IDD(3
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 physical medium attachment interface (port 8) receive PMA receive (see Figure 16) NO. 1 – 2,3 4 4 4 5 5 5 MIN MAX 16 16 UNIT tc(Mxx_RBC) tdrift(Mxx_RBC) Cycle time, receive byte clock 0 and 1 (Mxx_RCLK, Mxx_COL) Drift rate† of receive bye clock 0 and 1 tw(Mxx_RBC) tsu(Mxx_RXD) Pulse duration, Mxx_RCLK, Mxx_COL low or high Setup time, Mxx_RXD7–Mxx_RXD0 valid before Mxx_RCLK/COL↑ 2.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 transmit PMA transmit (see Figure 17) NO.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 GMII (port 8) Figures 18–20 show the timing for the 100-/1000-Mbit/s GMII when operating at 1000 Mbit/s. Both Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD7–MxxRXD0 is driven by the PHY on the falling edge of Mxx_RCLK. Mxx_RXD7–MxxRXD0 timing must be met during clock periods in which Mxx_RXDV is asserted.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PMA and GMII clock (see Figure 20) NO. 1 MIN MAX UNIT Pulse width low, Mxx_RFCLK 2.5 ns 2 tr(Mxx_GCLK) th(Mxx_GCLK) Pulse width high, Mxx_RFCLK 2.5 ns 3 tw(Mxx_GCLK) Cycle time, Mxx_RFCLK 8 ns PMA and GMII clock (see Figure 20) NO.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MII (ports 0–8) Figures 21–23 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMII operating at 100-Mbit/s. Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD3–Mxx_RXD0 is driven by the PHY on the falling edge of Mxx_RCLK. Mxx_RXD3–Mxx_RXD0 timing must be met during clock periods in which Mxx_RXDV is asserted.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MII transmit (see Figure 22) NO. MIN MAX Delay time, from Mxx_TCLK↑ to Mxx_TXD3–MxxTXD0 valid 5 15 ns 1 td(Mxx_TXD) td(Mxx_TXEN) Delay time, from Mxx_TCLK↑ to Mxx_TXEN valid 5 15 ns 1 td(Mxx_TXER) Delay time, from Mxx_TCLK↑ to Mxx_TXER valid 5 15 ns 1 UNIT 1 Mxx_TCLK Mxx_TXD3–Mxx_TXD0 Mxx_TXEN Mxx_TXER ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Figure 22.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 RDRAM interface RDRAM (see Figure 24) NO. 1 2, 3 4, 5 6, 8 7, 9 10, 11 MIN MAX UNIT tc(DX_CLK) tw(DX_CLK) Cycle time DTX_CLK, DRX_CLK 3.33 3.33 ns Pulse duration, DTX_CLK, DRX_CLK low or high 45% 55% tw(TICK) tsu(DBUS_DATA) Pulse duration, tick time 0.5 0.5 tc(DX_CLK) tcycle Setup time, DBUS_DATA before tick 0.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface The DIO interface is simple and asynchronous to allow easy adaptation to a range of microprocessor devices and computer system interfaces. DIO and DMA writes (see Figure 25) NO.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO and DMA reads (see Figure 26) NO.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 EEPROM interface For further information on EEPROM interface timing, refer to the 24C02 or 24C08 serial EEPROM data sheets. EEPROM writes (see Figure 27) NO.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 LED interface LED (see Figure 29) NO. 1 2 3 4 5 MIN tc(LED_CLK) tw(LED_CLK) Cycle time, LED_CLK tn(LED_CLK) tc(BURST) Number of LED_CLK pulses in burst tsu(LED_DATA) th(LED_DATA) Setup time, LED_DATA before LED_CLK↑ MAX 8 Pulse duration, LED_CLK high 4 24† 4687488‡ Cycle time, LED_CLK burst 6 Hold time, LED_DATA after LED_CLK↑ † During hard reset, LED_CLK runs continuously.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION The following load circuits and voltage waveforms show the conditions used for measuring switching characteristics. Test points are illustrated schematically on the load circuits. Reference points are plotted on the voltage waveforms.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION tr Input 20% tf 80% 47% 80% 47% VDD 20% 0 tPHL VOH Out-of-Phase Output 47% 47% VOL tPHL tPLH tPHL VOH In-Phase Output 47% 47% VOL Figure 33. Internal Push/Pull Output Propagation-Delay-Time Voltage Waveforms tr CMOS-Level Input 20% tf 80% 47% 80% 47% VDD 20% 0 CMOS tPLH LVCMOS/TTL Output CMOS tPHL 50% 1.3 V TTL tPLH VOH 50% 1.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION Input (active-low enable) Hi-Z 80% VDD 47% 20% Active 0 tPZH Output High 50% LVCMOS 1.3 V TTL VOH Hi-Z (forced low) tPZL Output Low Input (active-low enable) 50% LVCMOS 1.3 V TTL Hi-Z 80% Active 47% 20% Hi-Z (forced high) VOL VDD 0 tPHZ + Ion Output High 1 mA 0 mA tPLZ 0 mA Output Low 1 mA – Ion Figure 35.
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TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MECHANICAL DATA GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE 31,75 SQ 35,20 SQ 34, 80 1,27 26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Heat Slug 1,70 MAX 0,91 NOM Seating Plane 0,90 0,60 0,50 MIN 0,15 0,30 M 4073223/A 11/96 NOTES: A. All linear dimensions are in millimeters. B.
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PACKAGE OPTION ADDENDUM www.ti.com 4-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TNETX4090GGP OBSOLETE BGA GGP Pins Package Eco Plan (2) Qty 352 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.