Manual

220 Series Commercial Grade CF Product Manual v2.0Cactus Technologies

Bit 2 (SW Rst) This bit is set to 1 in order to force the card to perform an AT Disk controller Soft

Reset operation. This does not change the PC Card Conguration Registers (4.3.2

to 4.3.5) as a hardware Reset does. The card remains in Reset until this bit is reset

to ‘0’.

Bit 1 (-IEn) The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is

1, interrupts from the card are disabled. This bit also controls the Int bit in the

Conguration and Status Register. This bit is set to 0 at power on and Reset.

Bit 0 This bit is ignored by the card.

Bit 7 This bit is unknown.

Implementation Note:

Conicts may occur on the host data bus when this bit is provided by a Floppy Disk

Controller operating at the same addresses as the Industrial ATA product. Following

are some possible solutions to this problem for the PC Card implementation:

1. Locate the Industrial ATA product at a non-conicting address (i.e., Secondary

address (377) or in an independently decoded Address Space when a Floppy Disk

Controller is located at the Primary addresses).

2. Do not install a Floppy and an Industrial ATA product in the system at the same

time.

3. Implement a socket adapter that can be programmed to (conditionally) tri-

state D7 of I/0 address 3F7/377 when an Industrial ATA product is installed and

conversely to tri-state D6-D0 of I/O address 3F7/377 when a oppy controller is

installed.

4. Do not use the Industrial ATA product’s Drive Address register. This may be

accomplished by either a) If possible, program the host adapter to enable only

I/O addresses 1F0-1F7, 3F6 (or 170-177, 176) to the Industrial ATA product or b)

if provided use an additional Primary/Secondary conguration in the Industrial

ATA product that does not respond to accesses to I/O locations 3F7 and 377.

With either of these implementations, the host software must not attempt to use

information in the Drive Address Register.

Bit 6 (-WTG) This bit is 0 when a write operation is in progress, otherwise, it is 1.

Bit 5 (-HS3) This bit is the negation of bit 3 in the Drive/Head register.

Bit 4 (-HS2) This bit is the negation of bit 2 in the Drive/Head register.

This register is provided for compatibility with the AT disk drive interface. It is recommended

that this register not be mapped into the host’s I/O space because of potential conicts on Bit

7. The bits are dened as follows:

4.5.11. Card (Drive) Address Register

(Address 3F7[377]; Oset Fh)

D7 D6 D5 D4 D3 D2 D1 D0

X -WTG -HS3 -HS2 -HS1 -HS0 -nDS1 -nDS0