Owner manual

300/300-P Series Industrial Grade SSD Product Manual v2.0Cactus Technologies

Table 3-7 describes the I/O signals. Signals whose source is the host are designated as inputs while

signals that the SSD sources are outputs. The SSD logic levels conform to those specied in the ANSI

ATA Specication.

Signal Description

3.2.

Signal Name Dir. Description

A2—A0

A[2:0] is used to select the one of eight registers in the Task File.

-PDIAG

I/O

This input/output is the Pass Diagnostic signal in the Master/Slave

handshake protocol.

-DASP

I/O

This input/output is the Disk Active/Slave Present signal in the

Master/Slave handshake protocol.

-CS0, -CS1

-CS0 is the chip select for the task le registers while -CS1 is used to

select the Alternate Status Register and the Device Control Register.

-CSEL

This internally pulled up signal is used to congure this device

as a Master or a Slave. When this pin is grounded, this device

is congured as a Master. When the pin is open, this device is

congured as a Slave.

D15—D00

I/O

These lines carry the Data, Commands and Status information

between the host and the controller. D00 is the LSB of the Even Byte

of the Word. D08 is the LSB of the Odd Byte of the Word. All Task

File operations occur in byte mode on the low order bus D00-D07

while all data transfers are 16 bits using D00-D15.

GND

Ground.

-IORD/-HDMARDY/

HSTROBE

This is an I/O Read strobe generated by the host for PIO data-in and

this signal.

-HDMARDY is a ow control signal for UDMA data-in transfers.

This signal is asserted by the host to indicate to the device that it is

ready to accept data. The host may negate this signal to pause the

trasnfer.

HSTROBE is a strobe signal generated by the host for UDMA data-

out transfers. Data is transferred on both edges of this signal.

Table 3-7. Signal Description