Owner manual
300/300-P Series Industrial Grade SSD Product Manual v2.0Cactus Technologies
®
16
ATA Registers
4.2.
4.2.1. Data Register (Address-1F0[170])
The Data Register is a 16-bit register, and it is used to transfer data blocks between the SSD data
buer and the Host.
4.2.2. Error Register (Address-1F1[171]; Read Only)
This register contains additional information about the source of an error when an error is indicated
in bit 0 of the Status register. The bits are dened as follows:
D7 D6 D5 D4 D3 D2 D1 D0
BBK UNC 0 IDNF 0 ABRT 0 AMNF
Bit 7 (BBK) This bit is set when a Bad Block is detected.
Bit 6 (UNC) This bit is set when an Uncorrectable Error is encountered.
Bit 5 This bit is 0.
Bit 4 (IDNF) The requested sector ID is in error or cannot be found.
Bit 3 This bit is 0.
Bit 2 (Abort) This bit is set if the command has been aborted because of a status condition:
(Not Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1 This bit is 0.
Bit 0 (AMNF) This bit is set in case of a general error.
4.2.3. Feature Register (Address-1F1[171]; Write Only)
4.2.4. Sector Count Register (Address-1F2[172])
This register provides information regarding features of the SSD that the host can utilize.
This register contains the number of sectors of data requested to be transferred on a read or write
operation between the host and the SSD. If the value in this register is zero, a count of 256 sectors
is specied. If the command was successful, this register is zero at command completion. If not
successfully completed, the register contains the number of sectors that need to be transferred in
order to complete the request.