User guide
900S Series Industrial Grade CFast Product Manual v2.0Cactus Technologies
®
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The communication to or from the CFast card is done using FIS. Legacy ATA protocol is supported
by using the legacy mode dened in the SATA specications. In this mode, the FIS has dened elds
which provide all the necessary ATA task le registers for control and status information. The Serial
ATA interface does not support Primary/Secondary or Master/Slave congurations. Each SATA
channel supports only one SATA device, with the register selection as dened by the ATA standard.
ATA Task File Denitions
4.1.
ATA Drive Register Set
Denition and Protocol04
The following sections describes the usage of the ATA task le registers. Note that the Alternate
Status Register of legacy ATA is not dened for SATA drives.
4.1.1. Data Register
The Data Register is a 16-bit register, and it is used to transfer data blocks between the SSD data
buer and the Host.
4.1.2. Error Register
This register contains additional information about the source of an error when an error is indicated
in bit 0 of the Status register. The bits are dened as follows:
D7 D6 D5 D4 D3 D2 D1 D0
BBK UNC 0 IDNF 0 ABRT 0 AMNF
Bit 7 (BBK) This bit is set when a Bad Block is detected.
Bit 6 (UNC) This bit is set when an Uncorrectable Error is encountered.
Bit 5 This bit is 0.
Bit 4 (IDNF) The requested sector ID is in error or cannot be found.
Bit 3 This bit is 0.
Bit 2 (Abort) This bit is set if the command has been aborted because of a status condition:
(Not Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1 This bit is 0.
Bit 0 (AMNF) This bit is set in case of a general error.
4.1.3. Feature Register
This register provides information regarding features of the SSD that the host can utilize.