Specifications

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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

This product has

inued.

Si3220/25

Si3200/02

DUAL PROSLIC

PROGRAMMABLE CMOS SLIC/CODEC

Features

Applications

Description

The Dual ProSLIC

is a series of low-voltage CMOS devices that integrate both

SLIC and codec functionality into a single IC to provide a complete dual-channel

analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI

specifications. The Si3220 includes internal ringing generation to eliminate

centralized ringers and ringing relays, and the Si3225 supports centralized ringing

for long loop and legacy applications. On-chip subscriber loop and audio testing

allows remote diagnostics and fault detection with no external test equipment or

relays. The Si3220 and Si3225 operate from a single 3.3 or 5 V supply and

interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200/2 linefeed

ICs perform all high-voltage functions and operate from a 3.3 or 5 V supply as well

as single or dual battery supplies up to 100 V (Si3200) or 125 V (Si3202). The

Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the

Si3200/2 is available in a thermally-enhanced 16-pin small outline (SOIC) package.

Functional Block Diagram

 Performs all BORSCHT functions

 Ideal for applications up to 18 kft

 Internal balanced and unbalanced ringing

(Si3220)

 External bulk ringer support (Si3225)

 Software-programmable parameters:

Ringing frequency, amplitude, cadence,

and waveshape (Si3220)

Two-wire ac impedance

Transhybrid balance

DC current loop feed

Loop closure and ring trip thresholds

Ground key detect threshold

 Automatic switching of up to three battery

supplies

 On-hook transmission

 Loop or ground start operation with

smooth/abrupt polarity reversal

 Modem/fax tone detection

 DTMF generation/decoding

 Dual tone generators

 A-Law/µ-Law, linear PCM

companding

 PCM and SPI bus digital interfaces

with programmable interrupts

 GCI mode support

 3.3 or 5 V operation

 GR-909 loop diagnostics

 Audio diagnostics with loopback

 12 kHz/16 kHz pulse metering

(Si3220)

 FSK caller ID generation

 Lead-free/RoHS-compliant

 Digital loop carriers

 Central Office telephony

 Pair gain remote terminals

 Wireless local loop

 Private Branch Exchange (PBX) systems

 Cable telephony

 Voice over IP/voice over DSL

 ISDN terminal adapters

text

DAC

ADC

Linefeed

Control

Linefeed

Monitor

DAC

ADC

Linefeed

Control

Linefeed

Monitor

SLIC A

SLIC B

Codec A

Codec B

DSP

SPI

Control

Interface

PCM /

GCI

Interface

PLL

Si3220/25

Linefeed

Interface

Linefeed

Interface

2-Wire AC

Impedance

Hybrid Balance

Pulse Metering

Subscriber Line

Diagnostics

DTMF Decode

Programmable

Audio Filters

Gain Adjust

Dual Tone

Generators

Modem Tone

Detection

Ringing

Generator

& Ring Trip

Sense

Loop Closure,

& Ground Key

Detection

FSK

Caller ID

Relay Drivers

SCLK

SDO

SDI

DTX

DRX

FSYNC

INT RESET

PCLK

TIP

Channel A

RING

TIP

RING

Channel B

Si3200/2

U.S. Patent #6,567,521

U.S. Patent #6,812,744

Other patents pending

Ordering Information

See “Dual ProSLIC Selection

Guide” on page 110.

Part Number Ringing

Method

Si3220 Internal

Si3225 External

Ringer

Summary of content (112 pages)

PAGE 1
S i 3 2 2 0/25 S i 3 2 0 0/02 D U A L P RO S L I C ® P ROGRAMMABLE CMOS SLIC/C ODEC Features     Performs all BORSCHT functions  Ideal for applications up to 18 kft Internal balanced and unbalanced ringing   (Si3220) External bulk ringer support (Si3225)  Software-programmable parameters:  Ringing frequency, amplitude, cadence,  and waveshape (Si3220) Two-wire ac impedance  Transhybrid balance  DC current loop feed  Loop closure and ring trip thresholds  Ground key detect thresh
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T be his en p r di od sc u o n ct tin ha ue s d. Si3220/25 Si3200/02 2 Preliminary Rev. 1.
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Si3220/25 Si3200/02 TABLE O F C ONTENTS Section Page T be his en p r di od sc u o n ct tin ha ue s d. 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.
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Si3220/25 Si3200/02 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information1 Parameter Symbol Test Condition Min Max Unit –0.5 6.0 V –20 +20 mA Si3220/Si3225 Supply Voltage VDD1VDD4 STIPAC, STIPDC, SRINGAC, SRINGDC Current IIN –10 +10 mA Input Voltage, Digital Pins VIND –0.3 VDDD+0.3 V T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 Table 1. Absolute Maximum Ratings and Thermal Information1 (Continued) Parameter High Battery Supply Voltage Symbol Test Condition Min Max Unit VBATH Continuous –130 0.4 V 10 ms –135 0.4 V VBAT, VBATL Continuous VBATH 0.4 V TIP or RING Voltage VTIP, VRING Continuous –130 0.4 V Pulse < 10 us VBATH–15 0.4 V Pulse < 4 us VBATH–35 0.4 V T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 Table 2. Recommended Operating Conditions Parameter Symbol Test Condition Min* Typ Max* Unit Ambient Temperature TA K/F-Grade 0 25 70 oC Ambient Temperature TA B/G-Grade –40 25 85 oC VDD1–VDD4 3.13 3.3/5.0 5.25 V Supply Voltage, Si3200/Si3202 VDD 3.13 3.3/5.0 5.
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Si3220/25 Si3200/02 Table 3. 3.3 V Power Supply Characteristics1 (Continued) (VDD, VDD1 – VDD4 = 3.
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Si3220/25 Si3200/02 Table 3. 3.3 V Power Supply Characteristics1 (Continued) (VDD, VDD1 – VDD4 = 3.
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Si3220/25 Si3200/02 Table 4.
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Si3220/25 Si3200/02 Table 4. 5 V Power Supply Characteristics1 (Continued) (VDD, VDD1 – VDD4 = 5 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Test Condition Min Typ Max Unit IVBAT Sleep mode, RESET = 0, VBAT = –70 V — 125 — µA Open (high-impedance), VBAT = –70 V — 190 — µA Active on-hook standby, VBAT = –70 V — 700 — µA Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = –24 V — 4.7 + ILIM — mA — 8.
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Si3220/25 Si3200/02 Table 5. AC Characteristics (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Test Condition Min Typ Max Unit 2.5 Figure 6 — — — –85 — — –65 VPK — –87 –65 dB TX/RX Performance Overload Level Overload Compression Signal-to-(Noise + Distortion) Ratio2 Audio Tone Generator Signal-toDistortion Ratio2 Intermodulation Distortion Gain Accuracy 2 Attenuation Distortion vs. Freq. Group Delay vs.
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Si3220/25 Si3200/02 Table 5. AC Characteristics (Continued) (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Test Condition Idle Channel Noise6 PSRR from VDD1 – VDD4 PSRR from VBAT Typ Max Unit — 12 15 dBrnC Psophometric weighted 3 kHz flat RX and TX, dc to 3.4 kHz RX and TX, dc to 3.4 kHz Longitudinal Performance 200 Hz to 1 kHz 1 kHz to 3.4 kHz 200 Hz to 3.
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Si3220/25 Si3200/02 Table 6. Linefeed Characteristics (VDD, VDD1 – VDD4 = 3.13 to 5.
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Si3220/25 Si3200/02 Table 6. Linefeed Characteristics (Continued) (VDD, VDD1 – VDD4 = 3.13 to 5.
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Si3220/25 Si3200/02 Table 8. Si3200/2 Characteristics (VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter TIP/RING Pulldown Transistor Saturation Voltage Test Condition VOV VRING – VBAT (Forward) VTIP – VBAT (Reverse) ILIM = 22 mA, IABIAS = 4 mA1 ILIM = 45 mA, IABIAS = 16 mA1 VCM Min Typ Max Unit   3   — V V GND – VTIP (Forward) GND – VRING (Reverse) ILIM = 22 mA1 ILIM = 45 mA1   3   — V V T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 Table 10. DC Characteristics (VDD, VDD1–VDD4 = 3.3 V) (VDD, VDD1 – VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Symbol Test Condition Min Typ Max Unit VIH 0.7 x VDD — 5.25 V Low Level Input Voltage VIL — — 0.3 x VDD V High Level Output Voltage VOH IO = 4 mA VDD – 0.6 — — V Low Level Output Voltage VOL DTX, SDO, INT, SDITHRU: IO = –4 mA — — 0.
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Si3220/25 Si3200/02 Table 12. Switching Characteristics—SPI (VDD, VDD1 – VDD4 = 3.13 to 5.
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Si3220/25 Si3200/02 Table 13. Switching Characteristics—PCM Highway Interface (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF) Parameter Symbol PCLK Period Test Conditions tp Typ1 Max1 Units 122 — 3906 ns — — — — — — — — — 256 512 768 1.024 1.536 1.544 2.048 4.096 8.192 — — — — — — — — — kHz kHz kHz MHz MHz MHz MHz MHz MHz T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 tr tp tf PCLK th1 twfs tsu1 FSYNC tfs tsu2 th2 T be his en p r di od sc u o n ct tin ha ue s d. DRX td1 td2 td3 DTX Figure 2. PCM Highway Interface Timing Diagram Preliminary Rev. 1.
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Si3220/25 Si3200/02 Table 14. Switching Characteristics—GCI Highway Serial Interface (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter1 Symbol Test Conditions Min Typ Max Units PCLK Period (2.048 MHz PCLK Mode) tp — 488 — ns PCLK Period (4.
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Si3220/25 Si3200/02 tr tf tc PCLK th1 tfs tsu1 FSYNC tsu2 T be his en p r di od sc u o n ct tin ha ue s d. DRX th2 Frame 0, Bit 0 td1 td2 td3 Frame 0, Bit 0 DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR Preliminary Rev. 1.
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Si3220/25 Si3200/02 9 8 7 6 Fundamental Output Power 5 (dBm0) Acceptable Region 4 3 2.6 2 T be his en p r di od sc u o n ct tin ha ue s d. 1 0 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) Figure 6. Overload Compression Performance TX Attenuation Distortion 5 0 Gain (dB) −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 Frequency (Hz) TX Pass−Band Detail 0.4 0.2 Gain (dB) 0 −0.2 −0.4 −0.6 −0.
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Si3220/25 Si3200/02 RX Attenuation Distortion 5 0 Gain (dB) −5 −10 −15 −20 −25 −30 −40 −45 0 250 T be his en p r di od sc u o n ct tin ha ue s d. −35 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 Frequency (Hz) RX Pass−Band Detail 0.4 0.2 Gain (dB) 0 −0.2 −0.4 −0.6 −0.8 −1 −1.2 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 Frequency (Hz) Figure 8.
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Si3220/25 Si3200/02 TX Group Delay Distortion 1100 1000 900 Delay (us) 800 700 600 T be his en p r di od sc u o n ct tin ha ue s d. 500 400 300 200 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Frequency (Hz) Figure 9.
PAGE 25
Ibuf Off-chip Gm On-chip ZA Analog Zsynth Disable ZSDIS + + Decimation Filter THPF TX EQ TPGA D/A DLM3 Codec Loopback A/D Preliminary Rev. 1.3 Interpolation Filter Receive Path + ZD Decimation Filter H Interpolation Filter DLM2 + Modem Tone Detection RPGA Dual Tone Generator RX EQ To Ringer Circuit RHPF Hybrid Loopback + /A-law Expander DLM1 PCM Loopback Figure 11.
PAGE 26
Preliminary Rev. 1.3 RJ-11 SMD 6 5 4 3 2 1 J11 RJ-11 SMD TP1 RINGa_ext TIPa_ext TP3 TP4 TIPa RINGb_ext TIPb_ext VBATb RINGb TIPb Protection VBATa RINGa Protection TP5 TP6 TP7 TP8 TP2 1 6 5 4 3 2 1 1 J1 1 1 1 1 1 RINGb TIPb C13 10n 100V C3 10n 100V RINGa TIPa C30 0.1u 100V R22 0 C24 0.1u 10V U2 Si3200 TIP ITIPP NC ITIPN RING THERM VBAT IRINGP VBATH IRINGN VBATL NC GN D NC VDD BATSEL 16 15 14 13 12 11 10 9 VBATH R23 15 VBATH VBLO C31 0.1u 100V VDD VBLO C23 0.
PAGE 27
RRDa VDD Ring B TP4 RRDb VDD TP3 Tip B Ring A TP2 RJ-11 SMD 6 5 4 3 2 1 J11 RJ-11 SMD 1 TP1 Tip A 3 1 8 DPDT K2 DPDT 10 10 1 8 3 K1 7 4 9 2 RINGa TIPa RINGb_ext TIPb C13 10n 100V RINGb Protection TIPb_ext C3 10n 100V C30 R24 15 C32 0.1u 100V C24 1 2 3 4 5 6 7 8 TIP NC RING VBAT VBATH VBATL GND VDD U2 ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL 16 15 14 13 12 11 10 9 C2 R6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 40.
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Si3220/25 Si3200/02 2. Bill of Materials Table 15. Si3220 + Si3200 External Component Values Component Value Function C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac-sensing inputs. C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% C5, C6, C15, C16 1 µF, 6.3 V, X7R, ±20% TIP/RING compensation capacitors. Low-pass filter capacitors to stabilize differential and common-mode SLIC feedback loops. C30–C33 0.1 µF, 100 V, Y5V Decoupling for battery voltage supply pins. C20–C25 0.
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Si3220/25 Si3200/02 Table 17. Si3225 + Si3200 External Component Values Component Value Function C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inputs. C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% C5, C6, C15, C16 1 µF, 6.3 V, X7R, ±20% TIP/RING compensation capacitors. Low-pass filter capacitors to stabilize differential and common mode SLIC feedback loops. C301, C311, C32, C33 0.1 µF, 100 V, Y5V Decoupling for battery voltage supply pins. C20–C25 0.
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Si3220/25 Si3200/02 3. Functional Description A complete audio transmit and receive path is integrated, including DTMF generation and decoding, tone generation, modem/fax tone detection, programmable ac impedance synthesis, and programmable transhybrid balance and programmable gain attenuation. These features are softwareprogrammable providing a single hardware design to meet international requirements.
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Si3220/25 Si3200/02 3.2. Power Supply Sequencing Note: This section applies to Si3200 revision E only. To ensure proper operation, the following power sequencing guidelines should be followed: VDD should be allowed to reach its steady state voltage at least 20 ms before VBATH is allowed to begin to ramp to its desired voltage.  Transients and oscillations with a dv/dt above 10 V/ µs on the VDD and VBATH supplies should always be avoided.  The ramp-up time for VDD should be in the range of 2 ms to 20 ms.
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Si3220/25 Si3200/02 battery supply that is provided. Because the battery supply depends on the state of the input supply (i.e., charging, discharging, or battery backup mode), the user must decide how much loop current is required and determine the maximum loop impedance that can be driven based on the battery supply provided. The minimum battery supply required can be calculated with the following equation: V BAT  V OC + V CM + V OV See "3.14.3.
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Si3220/25 Si3200/02 3.3.2. Linefeed Operation States The linefeed interface includes eight different operating states as shown in Table 18. The linefeed register settings (LF[2:0], linefeed register) are also listed. The open state is the default condition in the absence of any pre-loaded register settings. The device may also automatically enter the open state if excess power consumption is detected in the Si3200/2. See "3.8. Power Monitoring and Power Fault Detection" on page 37 for more details.
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Si3220/25 Si3200/02 Table 19. Register and RAM Locations for Linefeed Control Parameter Register/ RAM Mnemonic Register/RAM Bits Programmable Range LSB Size Effective Resolution Linefeed LINEFEED LF[2:0] See Table 18 N/A N/A Linefeed Shadow LINEFEED LFS[2:0] Monitor Only N/A N/A RLYCON BATSEL VBATH/VBATL N/A N/A Loop Current Limit ILIM ILIM[4:0] 18–45 mA 0.875 mA 0.875 mA On-Hook Line Voltage VOC VOC[14:0] 0 to 63.3 V 4.907 mV 1.
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Si3220/25 Si3200/02 70 60 5 50 3 1 VOCHTH 4 VOCLTH 40 2 6 T be his en p r di od sc u o n ct tin ha ue s d. Vtip/ring (V) 320 Ohms VOCDELTA 30 10 kOhms 2450 Ohms 1930 Ohms 1800 Ohms 20 10 0 0.005 0.01 0.015 0.02 0.025 Iloop (A) Figure 16.
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Si3220/25 Si3200/02 transition point. In the case of the discrete bipolar linefeed, since the source impedance is 320  both before and after the adaptive linefeed transition, the V/I curve exhibits no discontinuity at the transition points when VOCDELTA = 0. 3.4.3. Off-Hook to On-Hook Transition Load lines of 10 k, 1930  and 1800  are shown in Figure 16.
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Si3220/25 Si3200/02 0 mA 24 mA IRING -0 V ILIM = 24 mA -40 V T be his en p r di od sc u o n ct tin ha ue s d. -20 V VOCLTH 6 40  -48 V VOC DELTA -80 V 320  VOCHTH V RING Figure 17. Ground Start VRING/IRING Behavior 3.6. Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL register bit. This bit automatically resets upon completion of the calibration cycle.
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Si3220/25 Si3200/02 Table 21. Register and RAM Locations Used for Loop Monitoring Parameter Register/RAM Mnemonic Register/RAM Bits Measurement Range LSB Size Effective Resolution VLOOP VLOOP[15:0] 0 to 64.07 V 64.07 to 160.173 V 4.907 mV 251 mV 628 mV VTIP VTIP[15:0] 0 to 64.07 V 64.07 to 160.173 V 4.907 mV 251 mV 628 mV VRING VRING[15:0] 0 to 64.07 V 64.07 to 160.173 V 4.
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Si3220/25 Si3200/02 3.8.1. Transistor Power Equations (Using Discrete Transistors) 3.8.3. Power Filter and Alarms When using the Si3220 or Si3225 with discrete bipolar transistors, it is possible to control the total power of the solution by individually regulating the power in each discrete transistor. Figure 18 illustrates the basic transistor-based linefeed circuit for one channel. The power dissipation of each external transistor is estimated based on the A/D sample values.
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Si3220/25 Si3200/02 When the THERM pin is connected from the Si3220 or Si3225 to the Si3200/2 (indicating the presence of an Si3200/2), the resolution of the PTH12 and PSUM RAM locations is modified from 498 µW/LSB to 1059.6 µW/ LSB. Additionally, the THERMAL value must be modified to accommodate the Si3200/2. For the Si3200/2, THERMAL is typically 0.7 s, assuming the exposed pad is connected to the recommended ground plane as stated in Table 1 on page 4.
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Si3220/25 Si3200/02 Table 22. Register and RAM Locations Used for Power Monitoring and Power Fault Detection Register/ RAM Mnemonic Register/RAM Bits Measurement Range Resolution PSUM PSUM[15:0] 0 to 34.72 W 1059.6 µW Si3200/2 Power Alarm Interrupt Pending IRQVEC3 PQ1S N/A N/A Si3200/2 Power Alarm Interrupt Enable IRQEN3 PQ1E N/A N/A Q1/Q2 Power Alarm Threshold (discrete) Q1/Q2 Power Alarm Threshold (Si3200/2) PTH12 PTH12[15:0] 0 to 16.319 W 0 to 34.72 W 498 µW 1059.
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Si3220/25 Si3200/02 3.9. Automatic Dual Battery Switching The Dual ProSLIC chipsets provide the ability to switch between several user-provided battery supplies to aid thermal management. Two specific scenarios where this method may be required follow: Ringing to off-hook state transition (Si3220): During the on-hook operating state, the Dual ProSLIC chipset must operate from the ringing battery supply to provide the desired ringing signal when required.
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Si3220/25 Si3200/02 Table 23. Register and RAM Locations Used for Battery Switching Register/RAM Mnemonic Register/RAM Bits Programmable Range Resolution (LSB Size) High Battery Detect Threshold BATHTH BATHTH[14:7] 0 to 160.173 V* 628 mV (4.907 mV) Low Battery Detect Threshold BATLTH BATLTH[14:7] 0 to 160.173 V* 628 mV (4.
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Si3220/25 Si3200/02 When generating a high-voltage ringing amplitude using the Si3220, the power dissipated during the OHT state typically increases due to operating from the ringing battery supply in this mode. To reduce power, the chipset provides the ability to accommodate up to three separate battery supplies by implementing a secondary battery switch using a few low-cost external components as illustrated in Figure 20. using the switch internal to the Si3200/2.
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Si3220/25 Si3200/02 3.10. Loop Closure Detection Loop closure detection is required to accurately signal a terminal device going off-hook during the Active, OnHook Transmission (forward or reverse polarity), and ringing linefeed states. The functional blocks required to implement a loop closure detector are shown in Figure 21, and the register set for detecting a loop closure event is provided in Table 25.
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Si3220/25 Si3200/02 Table 25. Register and RAM Locations Used for Loop Closure Detection Parameter Register/RAM Mnemonic Register/RAM Bits Programmable Range LSB Size Effective Resolution IRQVEC2 LOOPS Yes/No N/A N/A IRQEN2 LOOPE Yes/No N/A N/A LINEFEED LFS[2:0] Monitor only N/A N/A Loop Closure Detect Status LCRRTP LCR Monitor only N/A N/A Loop Closure Detect Debounce Interval LCRDBI LCRDBI[15:0] 0 to 40.96 s 1.25 ms 1.25 ms ILOOP ILOOP[15:0] 50.54 to 101.09 mA 3.
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Si3220/25 Si3200/02 The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LONGDBI. If the debounce interval is satisfied, the LONGHI bit is set to indicate that a valid ground key event has occurred. When the Si3220/25 detects a ground key event, the linefeed automatically transitions from the TIP-OPEN (or RING-OPEN) state to the FORWARD-ACTIVE (or REVERSE-ACTIVE) state.
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Si3220/25 Si3200/02 Table 27. State Transitions During Ground Key Detection IQ2 IQ5 IQ6 Loop State LINEFEED State ILOOP (mA) ILONG (mA) LCR LONGHI CMHIGH 1 LOOP OPEN LFS = 3 (TIP-OPEN) 0 0 0 0 0 2 RING-GND LFS = 3 (TIP-OPEN) 22 –11 1 1 0 3 RING-GND LFS = 1 (FWD-ACTIVE) 22 –11 1 1 1 4 LOOP CLOSURE LFS = 1 (FWD-ACTIVE) 21 0 1 0 0 5 LOOP OPEN LFS = 1 (FWD-ACTIVE) 0 T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 Table 28. Register and RAM Locations Used for Ground Key Detection Register/ RAM Mnemonics Register/RAM Bits Programmable Range LSB Size Resolution Ground Key Interrupt Pending IRQVEC2 LONGS Yes/No N/A N/A Ground Key Interrupt Enable IRQEN2 LONGE Yes/No N/A N/A Ground Key Linefeed Shadow LINEFEED LFS[2:0] Monitor only N/A N/A Ground Key Detect Status LCRRTP LONGHI Monitor only N/A N/A Ground Key Detect Debounce Interval LONGDBI LONGDBI[15:0] 0 to 40.
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Si3220/25 Si3200/02 3.12. Ringing Generation The Si3220-based Dual ProSLIC® chipset provides a balanced ringing waveform with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are register-programmable. VRING VTERM – Figure 24.
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Si3220/25 Si3200/02 Table 29. Register and RAM Locations Used for Ringing Generation Parameter Register/RAM Register/RAM Bits Mnemonic Programmable Range Resolution (LSB Size) RINGCON TRAP Sinusoid/Trapezoid N/A Ringing Active Timer Enable RINGCON TAEN Enabled/Disabled N/A Ringing Inactive Timer Enable RINGCON TIEN Enabled/Disabled N/A Ringing Oscillator Enable Monitor RINGCON RINGEN Enabled/Disabled N/A Ringing Oscillator Active Timer RINGTALO/ RINGTAHI RINGTA[15:0] 0 to 8.
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Si3220/25 Si3200/02 3.12.1. Internal Sinusoidal Ringing 3.12.2. Internal Trapezoidal Ringing A sinusoidal ringing waveform is generated by the onchip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated at a 1 kHz rate. The ringing generator is programmed via the RINGFREQ, RINGAMP, and RINGPHAS registers.
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Si3220/25 Si3200/02 3.14. Ringing Coefficients VRING The ringing coefficients are calculated in decimals for sinusoidal and trapezoidal waveforms. The RINGPHAS and RINGAMP hex values are decimal to hex conversions in 16-bit 2’s complement representations for their respective RAM locations. RING Si3220 DC Offset TIP GND VTIP To obtain sinusoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to a 24-bit 2’s complement value. The lower 12 bits are placed in RINGFRLO bits 14:3.
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Si3220/25 Si3200/02 3.14.2. External Unbalanced Ringing The Si3225 supports centralized, battery-backed unbalanced ringing schemes by providing a ringing relay driver as well as inputs from an external ring trip circuit. Using this scheme, line-card designers can use the Dual ProSLIC chipset in existing system architectures with minimal system changes. 3.14.3. Linefeed Overhead Voltage Considerations During Ringing 3.14.4.
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Si3220/25 Si3200/02 3.15.1. Ringtrip Timeout Counter The Dual ProSLIC incorporates a ringtrip timeout counter, RTCOUNT, that will monitor the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter a sufficient amount of time (RTCOUNT x 1.25 ms/LSB) for the mode to switch to On-hook Transmission or Active.
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Si3220/25 Si3200/02 Table 30. Recommended Values for Ring Trip Registers and RAM Addresses1 Ringing Method Ringing Frequency DC Offset Added? RTPER RTACTH RTDCTH Yes No 800/fRING 800/fRING 2(800/ fRING) 2(800/ fRING) 800/fRING 2(800/ fRING) 221 x RTPER 1.59 x VRING,PK x RTPER 0.577(RTPER x VOFF) 32767 221 x RTPER 0.577(RTPER x VOFF) 1.59 x VRING,PK x RTPER 32767 32767 0.067 x RTPER x VOFF 32767 0.
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Si3220/25 Si3200/02 VDD VCC Si3220/ Si3225 3 V/5 V Relay (polarized or non-polarized) Relay Driver Logic RRDa/b TRD1a/b TRD2a/b T be his en p r di od sc u o n ct tin ha ue s d. The Si3220 can also add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state.
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Si3220/25 Si3200/02 VCC VDD Si3220/ Si3225 Polarized relay IDRV Q1 RDRV T be his en p r di od sc u o n ct tin ha ue s d. RRDa/b TRD1a/b TRD2a/b Figure 29. Driving Relays with VCC > VDD The maximum allowable RDRV value can be calculated with the following equation:  V DD,MIN – 0.6 V   R RELAY    Q1,MIN  MaxR DRV = ------------------------------------------------------------------------------------------------- – R SOURCE V CC,MAX – 0.3 V Where Q1,MIN ~ 30 for a 2N2222. Table 32.
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Preliminary Rev. 1.3 LFS LF RRD RINGEN COUNTER1 COUNTER0 IRINGXSCAL 0 1 2 3 5 0 6 1 7 2 8 3 9 5 11 6 0 LFSDELAY 4 10 7 1 8 2 9 3 Off 10 4 OHT 11 5 0 6 2 8 Ringing 1 7 3 9 4 10 5 11 6 0 7 1 8 2 9 3 11 5 0 6 Ringing On 10 4 T be his en p r di od sc u o n ct tin ha ue s d. D Figure 30.
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Si3220/25 Si3200/02 VOFF VRING + 510  _ 806 k Relay RTRP BLkRING 806 k Si3225 Phone RING Si3200 Hook Switch Protection T be his en p r di od sc u o n ct tin ha ue s d. RRD TIP VDD Figure 31. Si3225 External Ring Trip Circuitry 3.16.1. Ringing Relay Activation During Zero Crossings timing sequence for a typical ringing relay control application.
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Si3220/25 Si3200/02 Setting the linefeed register to the opposite polarity immediately reverses (hard reversal) the line polarity. For example, to transition from Forward Active mode to Reverse Active mode changes LF[2:0] from 001 to 101. Polarity reversal is accommodated in the OHT and ground start modes. The POLREV bit is a read-only bit that reflects if the device is in polarity reversal mode.
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Si3220/25 Si3200/02 3.18. Two-Wire Impedance Synthesis Where: Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop thus minimizing the receive path signal reflected back onto the transmit path. The Dual ProSLIC chipset provides on-chip, digitally-programmable, two-wire impedance synthesis to meet return loss requirements against virtually any global two-wire impedance requirement.
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Si3220/25 Si3200/02 clocks are turned back ON, the IIR filter experiences a discontinuity in the input signal. By writing power-down register 124 (decimal) with 0xC0, the clocks to the digital synthesis filter are forced to be continuously ON at all times, and the TX audio path is also kept ON so that the IIR filter continues to run and receive continuous signal samples from the TX channel no matter what state the SLIC is in.
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Si3220/25 Si3200/02 8 kHz Clock 8 kHz Clock ZEROENn Zero Cross OSCnEN 16-Bit Modulo Counter OSCnTA Expire Zero Cross Logic ENSYNCn Two-Pole Resonant Register Oscillator Load Logic OSCnTI Expire to TX Path Enable Load Signal Routing to RX Path OSCnTA OSCnFREQ OSCnTAEN INT Logic OSnTIS OSCnTI REL* ROUTn OSCnAMP T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 To enable automatic cadence for tone generator 1, define the OSC1TA and OSC1TI registers and set the OSC1TAEN and OSC1TIEN bits. This enables each of the timers to control the state of the oscillator enable bit, OSC1EN. The 16-bit counter counts until the active timer expires, at which time the 16-bit counter resets to zero and begins counting until the inactive timer expires. The cadence continues until the user clears the OSC1TA and OSC1TIEN control bits.
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Si3220/25 Si3200/02 OSC1EN 0,1 ... ..., OSC1TA 0,1 ... ... ..., OSC1TI 0,1 ... ..., OSC1TA 0,1 ... ... Tone Gen. 1 Signal Output T be his en p r di od sc u o n ct tin ha ue s d. ENSYNC1 Figure 36. Tone Generator Timing Diagram First Ring Burst Message Type Channel Seizure Message Length Parameter 1 Message Header Parameter Type Mark Data Packet Parameter 2 Second Ring Burst Parameter n Message Body Data Length Data Content Figure 37.
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Si3220/25 Si3200/02 3.20.4. Tone Generator Interrupts Both the active and inactive timers can generate an interrupt to signal “on/off” transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the OS1TAE and OS1TIE bits. Timer interrupts for tone generator 2 are OS2TAE and OS2TIE. A pending interrupt for each of the timers is determined by reading the OS1TAS, OS1TIS, OS2TAS, and OS2TIS bits in the IRQVEC1 register. 3.21.
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Si3220/25 Si3200/02 3.22. Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "3.20.1. Tone Generator Architecture" on page 63 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz.
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Si3220/25 Si3200/02 Decimation Filter ADC 12/16 kHz Bandpass Peak Detector PMAMPTH – IBUF ZA ++ + DAC T be his en p r di od sc u o n ct tin ha ue s d. PMRAMP Pulse Metering DAC ±+ x+ Pulse Metering Oscillator Volume Clip Logic 7FFF or 0 8 kHz Figure 38. Pulse Metering Generation Block Diagram 3.23. DTMF Detection On-chip DTMF detection, also known as touch tone, is available in the Si3220 and Si3225. It is an in-band signaling system that replaces the pulsedial signaling standard.
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Si3220/25 Si3200/02 Table 40 outlines the hex codes corresponding to the detected DTMF digits. Table 40. DTMF Hex Codes Hex code 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 Table 41. 2100 Hz Level vs. RAM Hex Value TIP and RING Level Across 600 W (dBm) TX Path: RAM 410 (154) or RX Path: RAM 413 (157) (Hex) +3 0x838 0 0x420 –3 0x20a T be his en p r di od sc u o n ct tin ha ue s d. Digit The threshold for declaring the presence or absence of 2100 Hz energy should be based on Table 41.
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Si3220/25 Si3200/02 3.25.4. TXEQ/RXEQ Equalizer Blocks The TXEQ and RXEQ blocks (see Figure 11 on page 25) represent 4-tap filters that can be used to equalize the transmit and receive paths, respectively. The transmit path equalizer is controlled by the TXEQCO0TXEQCO3 RAM locations, and the receive path equalizer is controlled by the RXEQCO0-RXEQCO3 RAM locations. The Si322x Coefficient Generator software uses these filters in calculating the ac impedance coefficients for optimal ac performance.
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Si3220/25 Si3200/02 The receive path transfer function requirement, shown in Figure 8 on page 23, is very similar to the transmit path transfer function. The PCM data rate is 8 kHz; so, no frequencies greater than 4 kHz are digitally-encoded in the data stream. At frequencies greater than 4 kHz, the plot in Figure 8 is interpreted as the maximum allowable magnitude of spurious signals that are generated when a PCM data stream representing a sine wave signal in the range of 300 Hz to 3.
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Si3220/25 Si3200/02 3.27. Interrupt Logic 3.28. SPI Control Interface The Dual ProSLIC devices are capable of generating interrupts for the following events: The control interface to the Dual ProSLIC devices is a 4-wire SPI bus modeled after microcontroller and serial peripheral devices. The interface consists of a clock, SCLK, chip select, CS, serial data input, SDI, and serial data output, SDO.
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Si3220/25 Si3200/02 The control byte has the following structure and is presented on the SDI pin MSB first: 7 6 5 4 3 2 1 0 BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3] See Table 42 for bit definitions. Table 42. SPI Control Interface 6 74 BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is only valid for write operations since it would cause contention on the SDO pin during a read. T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 SDI0 SDI SDO CPU CS CS SDI SDO Channel 0 SDI1 Dual ProSLIC #1 Channel 1 SCLK SDITHRU SDI2 T be his en p r di od sc u o n ct tin ha ue s d. SPI Clock SDI CS Channel 2 SDI3 SDO Dual ProSLIC #2 Channel 3 SCLK SDITHRU SDI4 SDI14 SDI CS Channel 14 SDI15 SDO Dual ProSLIC #8 Channel 15 SCLK SDITHRU Figure 41. SPI Daisy-Chain Mode Preliminary Rev. 1.
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Si3220/25 Si3200/02 In Figure 42, the CID field is zero. As this field is decremented (in LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes through the entire chain. The odd SDIs are internal to the device and represent the SDI to SDI_THRU connection between channels of the same device.
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Si3220/25 Si3200/02 Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data indicates to the SPI state machine that eight more SCLK pulses follow to complete the operation. For a WRITE operation, the last eight bits are ignored.
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Si3220/25 Si3200/02 CS SCLK SDI CONTROL ADDRESS DATA [15:8] DATA [7:0] SDO Hi-Z CS SCLK SDI SDO T be his en p r di od sc u o n ct tin ha ue s d. Figure 47. RAM Write Operation via an 8-Bit SPI Port CONTROL ADDRESS xxxxxxxx xxxxxxxx DATA [15:8] DATA [7:0] Figure 48. RAM Read Operation via an 8-Bit SPI Port CS SCLK SDI SDO CONTROL ADDRESS Data [15:8] Data [7:0] Figure 49. RAM Write Operation via a 16-Bit SPI Port CS SCLK SDI CONTROL ADDRESS Data [15:8] SDO Figure 50.
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Si3220/25 Si3200/02 3.29. PCM Interface slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit. DTX returns to highimpedance on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB. This is based on the setting of the PCMTRI bit of the PCM Mode Select register. Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention.
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Si3220/25 Si3200/02 PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB T be his en p r di od sc u o n ct tin ha ue s d. DTX LSB HI-Z HI-Z MSB LSB Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0) PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX DTX MSB LSB MSB LSB HI-Z HI-Z Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) 3.30.
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Si3220/25 Si3200/02 PCLK FSYNC PCLK_CNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB HI-Z HI-Z T be his en p r di od sc u o n ct tin ha ue s d. DTX LSB MSB LSB Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC Preliminary Rev. 1.
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Si3220/25 Si3200/02 Table 43. µ-Law Encode-Decode Characteristics* 8 7 6 5 4 3 2 1 #Intervals X Interval Size 16 X 256 16 X 128 Value at Segment Endpoints 8159 . . . 4319 4063 Digital Code 16 X 64 16 X 32 16 X 16 16 X 8 16 X 4 15 X 2 __________________ 1 X 1 10000000b 8031 10001111b 4191 . . . 2143 2015 10011111b 2079 . . . 1055 991 10101111b 1023 . . . 511 479 10111111b 495 . . . 239 223 11001111b 231 . . . 103 95 11011111b 99 . . . 35 31 11101111b 33 . . .
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Si3220/25 Si3200/02 Table 44. A-Law Encode-Decode Characteristics1,2 Segment Number #intervals X interval size Value at segment endpoints 7 16 X 128 4096 3968 . . 2176 2048 5 4 3 2 1 16 X 64 Decode Level 10101010b 4032 10100101b 2112 . . . 1088 1024 10110101b 1056 . . . 544 512 10000101b 528 . . . 272 256 10010101b 264 . . . 136 128 11100101b 132 . . . 68 64 11110101b 66 . . . 2 0 11010101b 1 T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 3.31. General Circuit Interface The Dual ProSLIC devices also contain an alternate communication interface to the SPI and PCM control and data interface. The general circuit interface (GCI) is used for the transmission and reception of both control and data information onto a GCI bus. The PCM and GCI interfaces are both four-wire interfaces and share the same pins.
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Si3220/25 Si3200/02 handshaking bits, MR and MX. The C/I bits indicate status and command communication while the handshaking bits Monitor Receive, MR, and Monitor Transmit, MX, exchange data in the Monitor channel. Figure 55 illustrates the contents of a GCI highway frame. 3.31.1. 16-Bit GCI Mode In addition to the standard 8-bit GCI mode, the Dual ProSLIC devices also offer a 16-bit GCI mode for passing 16-bit voice data to the upstream host processor.
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Si3220/25 Si3200/02 125 s = 1 Frame FS CH0 CH1 CH2 CH3 Sub-Frame 16 6 1 1 16 16 T be his en p r di od sc u o n ct tin ha ue s d. 8 B1 M C/I MR MX B2 Unused Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode 1st Byte 2nd Byte 3rd Byte MX Transm itter MX MR Receiver MR ACK 1st Byte ACK 2nd Byte ACK 3rd Byte 125  s Figure 57. Monitor Handshake Timing 86 Preliminary Rev. 1.
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Si3220/25 Si3200/02 By correctly manipulating the MX and MR bits, a transmission sequence can continue from the beginning specified address until an invalid memory location is reached. To end a transmission sequence, the host processor must signal an End-of-Message (EOM) by placing the downstream MX and MR bits inactive for two consecutive frames. The transmission can also be stopped by the Dual ProSLIC by signaling an abort.
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Si3220/25 Si3200/02 Idle MR = 1 M X * LL Initial S tate T be his en p r di od sc u o n ct tin ha ue s d. MX 1s t By te Rec eiv ed MR = 0 MX A bort MR = 1 MX MX ABT A ny S tate MX MX Wait f or LL MR = 0 M X * LL M X * LL By te V alid MR = 0 M X * LL MX M X * LL MX New By te MR = 1 MX nth by te rec eiv ed MR = 1 M X * LL Wait f or LL MR = 0 MR : MR bit calcu lated and tran s m itted on d ata ups tream (D TX) line. MX: MX b it received d ata dow n s trea m (D R X) lin e.
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Si3220/25 Si3200/02 M R * M XR M XR Idle MR = 1 M R * M XR Wait MX = 1 M R * M XR A bort MX = 1 M R * RQT T be his en p r di od sc u o n ct tin ha ue s d. MR 1s t By te MX = 0 M R * RQT EOM MX = 1 MR M R * RQT nth By te ac k MX = 1 MR MR M R * RQT Wait f or ac k MX = 0 M R * RQT CLS /A B T A ny S tate MR : MR bit received on D R X line. MX: MX bit calculated and expected on D TX line. MXR : MX bit s am pled on D TX line. C LS: C ollis ion w ithin the m onitor data byte on D TX line.
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125  s 1 Frame $FF $91 $91 $FF $FF Preliminary Rev. 1.3 $FF $FF $81 $FF $FF $10 $FF $FF $91 $FF s ends addres s before data $91 $FF $FF $FF $FF $FF $FF $FF EOM Acknow ledge C ontents of C ontents of C ontents of C ontents of C ontents of R eg ister $10 R eg ister $10 R eg ister $11 R eg ister $11 R eg ister $12 (ig nored by host) EOM Signalled $FF Figure 60.
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Si3220/25 Si3200/02 Monitor Data Downstream $FF $FF $91 $91 $01 $01 $10 $10 125 s 1 Frame Data to be written to $10 Data to be written to $10 Data to be written to $11 Data to be written to $11 $FF $FF T be his en p r di od sc u o n ct tin ha ue s d. MX Downstream Bit MR Downstream Bit EOM Signalled Monitor Data Upstream $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF MX Upstream Bit MR Upstream Bit EOM Acknowledge = Acknowledgement of data reception Figure 61.
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Si3220/25 Si3200/02 3.31.3. Programming the Dual ProSLIC Using the Monitor Channel The Dual ProSLIC devices use the monitor channel to Transfer status or operating mode information to and from the host processor.
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Si3220/25 Si3200/02 monitor channel section. This section defines the functionality of the six C/I bits whether they are being transmitted to the GCI bus via the DTX pin (upstream) or received from the GCI bus via the DRX pin (downstream). The structure of the SC channel is shown in Figure 62. LSB MSB 7 6 5 4 3 2 1 0 CI2A CI1A CI0A CI2B CI1B CI0B MR MX The current state of the C/I bits is stored in a primary register, P.
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Si3220/25 Si3200/02 Receive New C/I Code = P? Yes No P: C/I Primary Register Contents Store in S S: C/I Secondary Register Contents T be his en p r di od sc u o n ct tin ha ue s d. Receive New C/I Code = S? Load C/I Register With New C/I Bits Yes No = P? Yes No Figure 63.
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Si3220/25 Si3200/02 might be set incorrectly. If this problem persists after the power alarm settings are verified, a system fault is probable, and the user should take measures to diagnose the problem. 3.31.10. Upstream (Transmit) SC Channel Byte The upstream SC channel byte looks similar to the downstream SC channel byte except that the information quickly transfers the most time-critical information from the Dual ProSLIC to the GCI bus.
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Si3220/25 Si3200/02 The interrupt information for channels A and B is a single bit that indicates that one or more interrupts might exist on the respective channel. Each of the individual interrupt flags (see registers 18–20) can be individually masked by writing the appropriate bit in registers 21–23 to ignore specific interrupts. When using the GCI mode, the user should verify that each of the desired interrupt bits are set so the upstream SC channel byte includes the required interrupt functions. 3.32.
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Si3220/25 Si3200/02 Table 52. Summary of Signal Generation and Measurement Tools Function Range Accuracy/Resolution Comments Signal Generation Tools DC Current Generation 18 to 45 mA 0.875 mA DC Voltage Generation 0 to 63.3 V 1.005 V Audio Tone Generation 200 to 3400 Hz — 4 to 15 Hz 16 to 100 Hz ±5% ±1% T be his en p r di od sc u o n ct tin ha ue s d. Ringing Signal Generation Measurement Tools 8-Bit dc/Low-Frequency Monitor A/D Converter High Range: 0 to 160.173 V 0 to 101.
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Si3220/25 Si3200/02 PEAK DETECT DIAGPK VTIP VRING DIAGDCCO VLOOP VLONG DIAGDC LPF ILOOP DIAGACCO ILONG VRING,EXT FULL WAVE RECTIFY LPF DIAGAC T be his en p r di od sc u o n ct tin ha ue s d. IRING,EXT Figure 64. SLIC Diagnostic Filter Structure 3.32.4. Measurement Tools VLONG 8-Bit monitor A/D converter. This 8-bit A/D converter monitors all dc and low-frequency voltage and current data from TIP to ground and RING to ground.
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Si3220/25 Si3200/02 Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on and off times of the ringing and pulse-metering signals. The tone generation oscillator can be used to program a time period for averaging specific measured test parameters.  Transmit audio path diagnostics filter. Transmit path audio diagnostics are facilitated by implementing a sixth-order IIR filter followed by peak detection and power estimation blocks.
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Si3220/25 Si3200/02     Line capacitance measurement. Implemented like the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized two-wire impedance of the Dual ProSLIC, the roll-off effect can be used to calculate the ac line capacitance. Ringing voltage verification.
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Si3220/25 Si3200/02 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 BATSELa TRD2a TRD1a RTRPa BLKRNG THERMa IRINGPa GND1 VDD1 ITIPPa IRINGNa ITIPNa SRINGDCa SRINGACa STIPACa STIPDCa BATSELa TRD2a TRD1a NC IRINGPa THERM a NC GND1 VDD1 ITIPPa IRINGNa ITIPNa SRINGDCa SRINGACa STIPACa STIPDCa 4.
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Si3220/25 Si3200/02 Pin Number(s) Symbol Input/ Output Description Si3225 9 9 IREF I IREF Current Reference. Connects to an external resistor to provide a highly-accurate reference current. Return path for IREF resistor should be routed to QGND pin. 17, 64 17, 64 STIPDCb, STIPDCa I TIP Sense. Analog current input senses dc voltage on TIP side of subscriber loop. 18, 63 18, 63 STIPACb, STIPACa I TIP Transmit Input. Analog input senses ac voltage on TIP side of subscriber loop.
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Si3220/25 Si3200/02 Pin Number(s) Si3220 Description NC No Internal Connection. Leave unconnected or connect to ground plane. 28, 52 RTRPb, RTRPa I External Ring Trip Sensing Input. Used to sense ring-trip condition when using centralized ring generator. Connect to low side of ring sense resistor. 30, 50 TRD2b, TRD2a O Test Relay Driver Output. Drives test relays for connecting loop test equipment. 31, 48 RRDb, RRDa O Ring Relay Driver Output.
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Si3220/25 Si3200/02 Pin Number(s) Symbol Input/ Output Description Si3225 46 46 SDITHRU O Serial Data Daisy Chain. Enables multiple devices to use a single CS for serial port control. Connect SDITHRU pin from master device to SDI pin of slave device. An internal pullup resistor holds this pin high during idle periods. 47 47 CS I Chip Select. Active low. When inactive, SCLK and SDI are ignored, and SDO is high impedance. When active, serial port is operational.
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Si3220/25 Si3200/02 5. Pin Descriptions: Si3200/2 Si3200/2 16-Lead SOIC (epad) TIP 1 16 ITIPP NC 2 15 RING 3 14 ITIPN THERM 4 13 IRINGP 5 12 IRINGN VBATL 6 11 GND 7 10 NC NC VDD 8 9 BATSEL T be his en p r di od sc u o n ct tin ha ue s d. VBAT VBATH Pin #(s) Symbol Input/ Output 1 TIP I/O TIP Output. Connect to the TIP lead of the subscriber loop. NC — No Internal Connection. Do not connect to any electrical signal. RING I/O RING Output.
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Si3220/25 Si3200/02 Symbol Input/ Output 12 IRINGN I Negative RING Current Control. Connect to the IRINGN lead of the Si3220 or Si3225. 13 IRINGP I Positive RING Current Drive. Connect to the IRINGP lead of the Si3220 or Si3225. 14 THERM O Thermal Sensor. Connect to THERM pin of Si3220 or Si3225. 15 ITIPN I Negative TIP Current Control. Connect to the ITIPN lead of the Si3220 or Si3225. 16 epad 106 Description T be his en p r di od sc u o n ct tin ha ue s d.
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Si3220/25 Si3200/02 6. Package Outline: 64-Pin TQFP T be his en p r di od sc u o n ct tin ha ue s d. Figure 65 illustrates the package details for the Dual ProSLIC. Table 53 lists the values for the dimensions shown in the illustration. Figure 65. 64-Pin Exposed Pad TQFP Table 53. Package Dimensions Symbol A A1 A2 b c Millimeters Symbol Millimeters Min Nom Max Min Nom Max — — 1.20 e 0.05 — 0.15 L 0.45 0.60 0.75 0.95 1.00 1.05 aaa — — 0.20 0.17 0.22 0.27 bbb — — 0.
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Si3220/25 Si3200/02 7. Package Outline: 16-Pin ESOIC Figure 66 illustrates the package details for the Si3200/2. Table 54 lists the values for the dimensions shown in the illustration. 16 9 h E H 0.010  1 8 B GAUGE PLANE L T be his en p r di od sc u o n ct tin ha ue s d. Bottom Side Exposed Pad 2.3 x 3.6 mm Detail F D C A e Seating Plane See Detail F A1  Weight: Approximate device weight is 0.15 grams. Figure 66.
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Si3220/25 Si3200/02 8.
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Si3220/25 Si3200/02 9.
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Si3220/25 Si3200/02 DOCUMENT CHANGE LIST Revision 1.1 to Revision 1.2 Updated power supply characteristics in Table 3 and Table 4.  Added note to Tables 15 and 17 to clarify SDO and DTX pulldown requirements when multiple Si3220/25s are connected to the same SPI or PCM bus.  Updated "9. Dual ProSLIC Selection Guide" on page 110.  Revision 1.2 to Revision 1.3 Added Si3202 125 V linefeed IC. T be his en p r di od sc u o n ct tin ha ue s d.  Preliminary Rev. 1.
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Si3220/25 Si3200/02 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 T be his en p r di od sc u o n ct tin ha ue s d. Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.