Hardware manual

45
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96630 Series
DS704-00012-1v0-E
(5) Operating Conditions of PLL
(V
CC
= AV
CC
= 2.7V to 5.5V, V
SS
= AV
SS
= 0V, T
A
= - 40°C to + 125°C)
Parameter Symbol
Value
Unit Remarks
Min Typ Max
PLL oscillation stabilization wait time t
LOCK
1 - 4 ms For CLKMC = 4MHz
PLL input clock frequency f
PLLI
4 - 8 MHz
PLL oscillation clock frequency f
CLKVCO
56 - 108 MHz
Permitted VCO output
frequency of PLL
(CLKVCO)
PLL phase jitter t
PSKEW
-5 - +5 ns
For CLKMC (PLL input
clock) ≥ 4MHz
PLL output
Deviation time from the ideal clock is assured per cycle out of 20,000 cycles.
Ideal clock
Slow
t1
t1
t2 t3 tn-1
tn-1
tn
tn
t2
t3
Fast
Deviation
time
(6) Reset Input
(V
CC
= AV
CC
= 2.7V to 5.5V, V
SS
= AV
SS
= 0V, T
A
= - 40°C to + 125°C)
Parameter Symbol Pin name
Value
Unit
Min
Max
Reset input time
t
RSTL
RSTX
10 -
µs
Rejection of reset input time 1 -
µs
RSTX
0.2V
CC
0.2V
CC
t
RSTL