User Manual

3-1
June 1997
Part No. 001-3412-002
SECTION 3 PROGRAMMING
3.1 INTRODUCTION
DM3412 - The information in Section 3.2
describes synthesizer programming protocol. This
information can be used as a basis for designing the
synthesizer programming hardware and software
required.
3.2 SYNTHESIZER DATA PROTOCOL
3.2.1 GENERAL
Programming of the SA-7025 Synthesizer IC
(U811) is accomplished via the 3-line bus; DATA,
CLOCK and SYNTH EN. Three 24-bit words (D, B
and A0) are required to load the synthesizer. The D
and B words contain four address bits each and the A0
has a 1-bit address. When the A0 word is loaded, the
synthesizer frequency acquisition is initiated (see Fig-
ure 3-1).
Receive Bandwidth 380-512 MHz
Transmit Bandwidth 380-512 MHz
First IF 52.95 MHz
Second IF 450.0 kHz
First LO Injection 432.95-564.95 MHz*
Second LO Injection 52.5 MHz**
TCXO Frequency 17.50 MHz
Resolution 6.25 or 10 kHz
Loop Comparison Freq. 50 kHz (FCM)
* High Side Injection
** Low Side Injection
Figure 3-1 24-BIT SYNTHESIZER SERIAL DATA STREAM
LSB (00)
Data
Clock
Synth En
MSB (23)
D23 D22 D21 D20 - D00D01-
Clock (max.)
Synth Enable (min)
D00 - D23
1 MHz
250 ns (for D, C, and B words)
D, B and A0 words