User's Manual

SECTION 6
CIRCUIT DESCRIPTION
6-1
001-4008-101/102
6.1 OVERVIEW
Section 6 describes the circuit operation of the logic board. This section is intended for use by engineering
and service personnel.
6.2 CIRCUIT DESCRIPTION
Refer to Figure 6-1 for the block diagram of the Integra-TR Logic Board.
6.2.1 MICROPROCESSOR CIRCUIT
The microprocessor contains two Z84015 CMOS low power Intelligent Peripheral Controllers (IPC). Each
IPC is an 8-bit microprocessor integrated with CTC, SIO, PIO Clock Generator Controller and Watch Dog
Timer.
One of the Z84015s (U17) is used in the normal mode. The other Z84015 (U21) is used in the evaluation
mode and only the CTC, SIO and PIO sections are used. The CPU section is disabled.
The first Z84015 Clock Generator uses a 19.6608 MHz crystal that provides a CPU clock rate of 9.8304
MHz for both Z84015s. The 9.8304 MHz clock is further divided by 2 to feed all 8 CTC (4 in each Z84015).
The 64K-memory space of the Z84015 is divided into two blocks of 32k each. The lower 32K are used for
the firmware program and the upper 32K by the CMOS RAM (U18). The memory IC used for the program
is a CMOS FLASH (U22) with 1024 sectors of 128 bytes each.
The dual Z84015 circuit provides up to 8 Counter Timer Channels (CTC), 4 Serial Input/Output (SIO) and
32 Parallel In-put/Output (PIO) lines.
The CPU also provides the clock for the CPLD modem.
6.2.2 RS232
The RS232 IC (U15) is used to interface the application DE-9 connector to the SIO_B section of U17, and
the set-up DE-9 connector to the SIO_A section of U21. Two receivers remain enabled in sleep mode to
ensure fast wakeup.
6.2.3 MODEM
The modem section is used to interface the serial digital data to the transceiver.
The CPLD modem IC (U16) with a programmable Raise-Cosine filter (U10) operates in DRCMSK mode at
2400, 4800, 9600, and 19200 bits/sec. It incorporates a 7-bit hardware scrambler and uses Differential
(NRZI) encoding in DRCMSK mode to minimize data pattern-sensitivity. An electronic potentiometer U5B