User's Manual

Cambricon Technologies, MLU270-F Series Intelligent Processing Card User Manual
BAR2: 64MB prefetchable
BAR4: 64MB prefetchable
VF（4，64bit）：
BAR0: 256MB prefetchable
BAR2: 64MB prefetchable
BAR4: 64MB prefetchable
SMBus（8bit Address）
0x8E(write） 0x8F（read）
SMBUS Register is 32-bit wide, and below describes how to read a register（S:Slave，M:Master）：
Table 3 SMBUS Registers Reading
Direction
Bits
Content
M

S
1
START
M  S
8
SLAVE ADDRESS（Write）
S  M
1
ACK
M  S
8
REGISTER ADDRESS
S  M
1
ACK
M

S
1
RE START
M

S
8
SLAVE ADDRESS（Read）
S  M
1
ACK
S  M
8
DATA[7:0]
M  S
1
ACK
S  M
8
DATA[15:8]
M

S
1
ACK
S

M
8
DATA[23:16]
M  S
1
ACK
S  M
8
DATA[31:24]
M  S
1
NACK
M  S
1
STOP
Table 4 SMBUS Registers Description
Registers
Address
ACCESS
Description
Total Card Power
0x01
RO
Card Power consumption, Float Data, Unit W
Card Temperature
0x02
RO
Card Temperature, Float Data, Unit ℃
Chip Temperature
0x03
RO
Chip Temperature, Float Data, Unit ℃
power brake
0x05
WO
The main frequency is reduced to 25% of current
frequency when write 0x04,and restore to
pre-frequency when write 0x01
PCIE Vendor ID
and Device ID
0xA0
RO
[15:0] Vendor ID：0xCABC
[31:16] Device ID：0x0270
PCIE Sub-Vendor
ID and Sub-System
0xA1
RO
[15:0] Sub-Vendor ID：0xCABC
[31:16] Sub-System ID：for example 0x0018