LightWise Camera Series LW-5-S-1394 FireWireTM Smart Digital Imaging Module LW-5-S-1394-C – Color Available in Color Only. Specification and Users Guide Revision 2.1a Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
Table of Contents: 1 LW-5-S-1394 Introduction and Specification Overview 1.1 Product Description 1.2 Key Specifications 1.3 5 MP Image Sensor 1.4 Programming and User Configuration Options 1.5 Automatic Gain and Offset Correction 1.6 On-Board Image Buffer 1.7 Digital Panning & Scaling (Zoom) 1.8 JPEG Compression 1.9 Simplified Block Diagram 2 External Signals and Connectors 2.1 External Trigger Modes 2.2 External Connectors 3 Programming Guide 3.1 Top Level Memory Map 3.
Section 1: LW-5-S-1394-C Introduction and Specification Overview 1.1 Product Description The ISG LW-5-S-1394-C 'Smart' Digital Imaging Module provides a High Resolution area imaging solution with outstanding flexibility. The low cost and ease of integration into existing systems make it an excellent solution for a wide variety of applications. The interfaces to the Imager are industry standard to provide ease of integration into target systems.
1.2 Key Specifications • Resolution: 2592 x 1944 Pixels • Color only Available • Synchronous Shutter (Rolling) with advanced Trigger/Strobe capability • Data Rate: o Up to 15 Frames / second full resolution (2592 x 1944) o Up to 23 Frames / second partial frame (3 Mp – 2048 x 1536) o Up to 35 Frames / second partial frame (2 Mp – 1600 x 1200) o Up to 48 Frames / second partial frame (1.
• I/O for Triggers and Synchronization Flexibility • On-Board FPGA for User-Configurability o Customized Image Processing Capability o Customized Programmable I/O • High Quality Digital Panning and Zoom Capabilities. 1.2.1 ISG Color Image Processing Pipeline The LW-5-S-1394-C Color Imaging Module utilizes the ISG Hardware Image Processing Pipeline implemented in a XilinxTM FPGA. All color processing parameters are fully programmable by the user. Appendix B describes the image path. 1.
extraction, custom dynamic range mapping, JPEG Compression , etc. This method can also be used to configure the external I/O signals for custom functionality. Imaging Solutions Group is available for consulting with customers to design or enable custom configurations via the on-board FPGA. Contact sales@isgchips.com for information. 1.5 Automatic Gain and Offset Correction The LW-5-S-1394-C will provide on-board FPN correction through gain and offset compensation.
1.9 Simplified Block Diagram Image Conditioning and Control FPGA 5 MP CMOS Sensor With Onboard 12-bit ADC Timing Generator. 'Smart" Algorithm Space On-Board Image Buffers Up to 3 frames for Color for full resolution 2592 x 1944 Power Ckts., Regulators 1394a Controller/ Drivers/ Receivers 1394A (+12V in) OptoIsolators LW-5-S-1394-C Programmable I/O (with +5V, +12V out) Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
Section 2: Connectors and Trigger Modes Section 2.1: ISG Camera Module Triggering Description The ISG camera module provides a variety of triggering modes and flexibility using features internal to the FPGA controller as well as the sensor. For a more detailed description of the registers referenced in this document see the Programmers Reference manual. Register Description: Trigger Delay – A 16 bit value used to delay the start of integration from the active edge of the input trigger.
Trigger Mode A = IIDC Trigger Mode 0 Strobe Advance Shown Trigger Input Trigger Delay Sensor Integration Strobe Advance Strobe Output SensorReadout Note: In this mode the integratin time is determined by a register setting. Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
Trigger Mode A = IIDC Trigger Mode 0 Strobe Delay Shown Trigger Input Trigger Delay Sensor Integration Strobe Delay Strobe Output SensorReadout Note: In this mode the integratin time is determined by a register setting. Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
Trigger Mode A = IIDC Trigger Mode 0 Strobe Duration Shown Trigger Input Trigger Delay Sensor Integration Strobe Duration Strobe Output SensorReadout Note: In this mode the strobe duration is determined by the strobe duration registor. Also, the Strobe Duration mode bit must be enabled. Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
Trigger Mode B = IIDC Trigger Mode 1 Trigger Input Trigger Delay Sensor Integration Strobe Advance Strobe Output SensorReadout Note: In this mode the integratin time is determined by the trigger duration. Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
Trigger Mode C Trigger Input Trigger Delay Rerigger Delay Sensor Integration Strobe Advance Strobe Advance Strobe Output SensorReadout Note: In this mode the integratin time is determined by a register setting. Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
2.2 External Connectors 2.2.1 FirewireTM Connector: This interface is based on the industry standard 1394a specification. Two connectors are provided to allow camera daisy chaining. 2.2.
ISG Imager Module Ext I/O Header User Interface Trigger + Opto Isolator Input Circuit (Opto Trigger) 10V – 24 V DC, 20ma source max. Signal rate up to 60 KHZ Trigger - 4.7K Pull-up To 5V PWM Open Collector Buffer Strobe 4.7K Pull-up To 5V RS422 Driver TI SN65HVD3082ED Or equivalent See applications example on next page.
Applications Example: Using The RS422 Trigger Input 1) Preferred Method – RS422 Driver The optimal way to utilize this input to trigger the camera is to drive the RS422 Receiver in the camera with the corresponding driver device. The recommended driver is TI part number SN65HVD3082ED. This method provides a balanced, robust differential input. 2) Alternate Method - Driving the RS422 Trigger Input with Standard 3.
Section 3: Programming Guide 3.
3.2 Register Detail Note: Some data formats are given as (S/U # of integer bits. # of fractional bits). For example, S1.3 means the value can be either positive or negative with the first bit indicating the sign, one integer bit and three fractional bits. U0.8 means no sign bit (positive number), zero integer bits and eight fractional bits. Negative values must be programmed as 2’s complement. A format of Bn means a binary format with n bits used.
STRBM : Strobe Mode. These bits control the functionality of the Strobe output to the illumination system. STRBM[1:0] = 00 : Active high (Activated by trigger). STRBM[1:0] = 01 : Active Low (Activated by trigger). STRBM[1:0] = 10 : Always high (Not activated by trigger). STRBM[1:0] = 11 : Always low (Not activated by trigger). HTRIG : Host trigger bit. Asserted via 1394 interface. VIDEN : Video Enable bit. This bit is set after imager is initialized.
Address : 0x408 (TRGDLY) Data format : U16 Default Value: 00h 15 14 13 12 11 TRGDLY(15:8) 10 9 8 7 6 5 4 3 TRGDLY(7:0) 2 1 0 TRGDLY : This 16 bit Value is used to program a delay from the time trigger is received to when strobe is activated. A delay between 0 and 1.37s in 20.83us steps can be achieved. The default value is 0.
Address : 0x410 (RTGDLY) Data format : U16 Default Value: 00h 15 14 13 12 11 RTGDLY(15:8) 10 9 8 7 6 5 4 3 RTGDLY(7:0) 2 1 0 RTGDLY : trigger This 16 bit Value is used to program the delay between video frames in continues Mode. A delay between 0 and 341ms in 5.21us steps can be achieved. The default value is 0. Address : 0x414 (PWM) Data format : U8 Default Value : 80h 7 6 PWM : 5 4 3 PWM(7:0) 2 1 0 PWM Duty Cycle.
Address : 0x420 (VVDLY) Data format : B4 Default Value : 02h 7 6 5 4 3 not used VVDLY : 2 1 VVDLY(3:0) 0 Video Valid Delay. The value in this register is used to move the video relative to the video valid signal internal to the FPGA. Address : 0x448 (CLKCR) Data format : U5 Default Value: 0h 7 6 not used 5 4 INV 3 2 1 CLKDIV(3:0) 0 INV: When this bit is set, the sensor clock is inverted. CLKDIV : Clock Divider. The sensor base clock rate is 48Mhz for Micron and 48Mhz for IBIS.
Address : 0x818 (HCS) Data format : B2 7 6 5 4 3 2 not used 1 STAT 0 LOCK LOCK : Histogram lock out control. This bit is R/W 0 = Histogram values are updated at the end of each frame. 1 = Histogram values are NOT updated at the end of each frame. Lock out updates to read the Histogram results. Setting this bit also clears the status bit. STAT : Status bit is set at the end of a frame when the histogram is available. The status bit is cleared by setting the LOCK bit.
Address : 0x8b4 (LUTAD) Data format : U10 15 14 13 12 11 10 9 8 LUTAD[9:8] 4 3 LUTAD[7:0] 2 1 not used 7 6 5 0 LUTAD : LUT Address Register. Reads and writes from the LUT data register use the value in this register as the address into the LUT. Reads/Writes to the data register causes the value in this register to be incremented by 1. Hence, the LUTs can be loaded by successive writes to the data register. This register is R/W.
Section 4: Mechanical Information 4.1 Lens Mount A Case-Mount CS type (1.0” diameters with 12.5 mm spacing between the surface of the sensor and top of the lens-mount) lens mount is provided for both system configurations. C-Type Lenses: A five mm extender will change the CS to C-Type lens mount with 17.5 mm Back Focal Length. F-Type Lenses: Using the Cannon 50mm F-type FD series + the Canon "C-type to Ftype" adapter will covert the camera to F-type with 39.9 mm Back Focal Length. 4.
4.3 LW-5-S-1394-C Digital Imaging Module Dimensions 2.875” (73 mm) Front View 1” 1.625” (39 mm) CS Lens Mount (25.4mm) 2.0625” (52 mm) Mini-USB2.0 Connector For debug and development CPU Status Imaging Status LEDs FireWireTM Connector 2 Back View Trigger / Strobe Connector FireWireTM Connector 1 Screw holes for securing camera Female Tripod Socket 1.25” (31 mm) Bottom View 1.25” (31 mm) Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.
Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
4.4 Module Components: The ISG LW-5-S-1394-C Digital Imaging Module hardware design is partitioned into four separate boards: 1) Sensor, 2) Controller, 3) Power Management and 4) I/O boards. These boards are SMT type 2 (double sides) and are connected to each others as shown below: Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
4.5 Operating Conditions Measured Average Power Consumption via 1394 cable: 12V, 250 ma rms / 3.0W Ambient Operating Temperature Range: -10 to 45 C FCC and CE Qualification: In progress. Test results available upon request. Vibration and Shock Testing: In progress. Target specification: 7G rms (10Hz to 2000Hz) Random, Shock 70G. Test results available upon request. Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
5.0 ISG Firmware + FPGA Upgrade Process This process will use the ISG Camera Control GUI application software on the host PC, to update firmware and/or FPGA code on the ISG 1394 camera. The camera’s firmware/FPGA code is loaded through the 1394 interface using the ISG GUI. A customer wishing to do a firmware or FPGA upgrade should perform the following steps: 1) Extract, and copy the firmware/FPGA binary data files to a directory on your host PC. The files are named isgcpu_ccxx_xxxx.
9). After the camera is connected, you can right click in the top toolbar of the GUI and select “about isg camera system” to read the new version numbers. Trade Mark Note: FireWire™ is a registered trademark of Apple Inc Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
APPENDIX A: ISG Color Image Processing Pipeline Copyright, 2004 Imaging Solutions Group of NY, Inc., All Rights Reserved Revision 2.1 Subject to change without notice.
