User`s manual

70 CMX34GS cpuModule BDM-610000082 Rev A
Reset Status Register
The cpuModule has several different signals on board which can cause a system reset. If a reset occurs, the reset
status register can be used to see which reset or resets have been asserted on the cpuModule.
The user has the ability to see which resets have been asserted. Resets can also be cleared.
• Examine Resets: Reading from I/O port 0xEA8 will indicate if a reset has been asserted. If a 1 is read,
the corresponding reset has been asserted. If a 0 is read from the bit, the reset has not been asserted
• Clear Reset: Each reset can be cleared by writing a 1 to the selected bit of I/O port 0xEA8.
Thermal Trip
1 = reset asserted
0 = no reset
System Power
1 = reset asserted
0 = no reset
Memory Term. Power
1 = reset asserted
0 = no reset
Main Power
1 = reset asserted
0 = no reset
Utility Reset
1 = reset asserted
0 = no reset
CPU Core Power
1 = reset asserted
0 = no reset
Memory Power
1 = reset asserted
0 = no reset
Standby Power
1 = reset asserted
0 = no reset
Table 49 Reset Status I/O Address EA8h - Read Access
D7 D6 D5 D4 D3 D2 D1 D0
Thermal Trip
1 = clear reset
System Power
1 = clear reset
Memory Term. Power
1 = clear reset
Main Power
1 = clear reset
Utility Reset
1 = clear reset
CPU Core Power
1 = clear reset
Memory Power
1 = clear reset
Standby Power
1 = clear reset
Table 50 Reset Status I/O Address EA8h - Write Access
D7 D6 D5 D4 D3 D2 D1 D0